15 s/pdif control register (index 3ah), Cs4202 – Cirrus Logic CS4202 User Manual

Page 33

Advertising
background image

CS4202

DS549PP2

33

4.15

S/PDIF Control Register (Index 3Ah)

V

Validity. The V bit is mapped to the V bit (bit 28) of every sub-frame. If this bit is ‘clear’, the
signal is suitable for conversion or processing.

DRS

Double Rate S/PDIF. The DRS bit is mapped to bit 27 of the channel status block. This bit
controls support for optional higher sample rate transmission. The CS4202 does not support
double rate S/PDIF transmission, therefore DRS is a read-only bit and always returns ‘0’.

SPSR[1:0]

S/PDIF Sample Rate. The SPSR[1:0] bits are mapped to bits 24 and 25 of the channel status
block. These bits control the S/PDIF transmitter clock rate. The CS4202 only supports trans-
mission at the standard 48 kHz rate, therefore SPSR[1:0] are read-only bits and always
return ‘10’.

L

Generation Status. The L bit is mapped to bit 15 of the channel status block. For category
codes 001xxxx, 0111xxx and 100xxxx, a value of ‘0’ indicates original material and a value of
‘1’ indicates a copy of original material. For all other category codes the definition of the L bit
is reversed.

CC[6:0]

Category Code. The CC[6:0] bits are mapped to bits 8-14 of the channel status block.

PRE

Data Pre-emphasis. The PRE bit is mapped to bit 3 of the channel status block. If the PRE bit
is ‘set’, 50/15 µs filter pre-emphasis is indicated. If the bit is ‘clear’, no pre-emphasis is indi-
cated.

COPY

Copyright. The COPY bit is mapped to bit 2 of the channel status block. If the COPY bit is ‘set’
copyright is not asserted and copying is permitted.

/AUDIO

Audio / Non-Audio. The /AUDIO bit is mapped to bit 1 of the channel status block. If the
/AUDIO bit is ‘clear’, the data transmitted over S/PDIF is assumed to be digital audio. If the
/AUDIO bit is ‘set’, non-audio data is assumed.

PRO

Professional/Consumer. The PRO bit is mapped to bit 0 of the channel status block. If the

PRO bit is ‘clear’, consumer use of the audio control block is indicated. If the bit is ‘set’, pro-
fessional use is indicated.

Default

2000h

For a further discussion of the proper use of the channel status bits see application note AN22: Overview of Digital
Audio Interface Data Structures [3]

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

V

DRS SPSR1 SPSR0

L

CC6

CC5

CC4

CC3

CC2

CC1

CC0

PRE

COPY /AUDIO PRO

Advertising