Cirrus Logic CS4202 - Manual (Page 34)

CS4202
34 DS549PP2
4.16 Extended Modem ID Register (Index 3Ch)
ID[1:0] Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the
CS4202 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4202 is a secondary
audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins
and the current clocking scheme, see Table 18 on page 49.
Default x000h. This value indicates no supported modem functions.
The Extended Modem ID Register (Index 3Ch) is a read/write register that identifies the CS4202 modem capabilities.
Writing any value to this location issues a reset to modem registers (Index 3Ch-54h), including GPIO registers
(Index 4Ch - 54h). Audio registers are not reset by a write to this location.
4.17 Extended Modem Status/Control Register (Index 3Eh)
PRA GPIO Powerdown. When ‘set’, the PRA bit powers down the GPIO subsystem. When the
GPIO section is powered down, all outputs must be tri-stated and input Slot 12 should be
marked invalid when the AC-link is active. To use any GPIO functionality PRA must be
cleared first.
GPIO GPIO. When ‘set’, the GPIO bit indicates the GPIO subsystem is ready for use. When ‘set’,
input Slot 12 will also be marked valid.
Default 0100h
4.18 GPIO Pin Configuration Register (Index 4Ch)
GC[4:0] GPIO Pin Configuration. When ‘set’, the GC[4:0] bits define the corresponding GPIO pin as
an input. When ‘clear’, the corresponding GPIO pin is defined as an output. When the SDEN
bit in the Serial Port Control Register (Index 6Ah) is ‘set’, the GC[1:0] bits are read-only bits
and always return ‘0’. When SDEN is ‘clear’, the GC[1:0] bits function normally. Likewise,
when the SDO2 bit in the Serial Port Control Register (Index 6Ah) is 'set', the GC4 bit is a
read-only bit and always returns '0'. When SDO2 is 'clear', the GC4 bit functions normally.
The GC[3:2] bits have no such dependency.
Default 001Fh. This value corresponds to all GPIO pins configured as inputs.
After a Cold Reset or a modem Register Reset (see Extended Modem ID Register (Index 3Ch)), all GPIO pins are
configured as inputs. The upper 11 bits of this register always return ‘0’.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ID1 ID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 PRA 0 0 0 0 0 0 0 GPIO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 0 GC4 GC3 GC2 GC1 GC0