Cirrus Logic CS4202 - Manual (Page 49)

CS4202
DS549PP2 49
22 pF 22 pF
24.576 MHz
DGND
XTL_OUT
XTL_IN
Figure 17. External Crystal
External
Clock on
XTL_IN
ID1# ID0#
AC-Link
Timing
Mode
Codec
ID
Clock
Source
Clock
Rate
(MHz)
PLL
Active
Application Notes
Yes 1 1 Primary 0 External 24.576 No clock generator driving XTL_IN
Yes 1 0 Primary 0 External 14.31818 Yes
external clock source driving XTL_IN
loop filter connected to XTL_OUT
Yes 0 1 Primary 0 External 27.000 Yes
Yes 0 0 Primary 0 External 48.000 Yes
No 1 1 Primary 0 XTAL 24.576 No crystal connected to XTL_IN, XTL_OUT
No 1 0 Secondary 1 BIT_CLK 12.288 No
BIT_CLK from primary codec driving
BIT_CLK on all secondary codecs
No 0 1 Secondary 2 BIT_CLK 12.288 No
No 0 0 Secondary 3 BIT_CLK 12.288 No
Table 18. Clocking Configurations for the CS4202