Document Outline

• 1. Pin Descriptions
  • 1.1 Software Mode
  • 1.2 Stand-Alone Mode
• 2. Digital I/O Pin Characteristics
  • Table 1. Digital I/O Pin Power Rails
• 3. Typical Connection Diagram
  • Figure 1. CS4270 Typical Connection Diagram
• 4. Characteristics and Specifications
  • Specified Operating Conditions
  • Absolute Maximum Ratings
  • DAC Analog Characteristics
    • Figure 2. Output Test Load
    • Figure 3. Maximum Loading
  • DAC Combined Interpolation & Analog FIlter Response
  • ADC Analog Characteristics
  • ADC Digital Filter CharacteristicS
  • DC Electrical Characteristics
  • Digital SWITCHING Characteristics
  • Switching Characteristics - Serial Audio Interface
    • Figure 4. Master Mode, Left-Justified SAI
    • Figure 5. Slave Mode, Left-Justified SAI
    • Figure 6. Master Mode, I·S SAI
    • Figure 7. Slave Mode, I·S SAI
    • Figure 8. Master and Slave Mode, SCLK/SDIN
    • Figure 9. Format 0, Left-Justified up to 24-Bit Data
    • Figure 10. Format 1, I·S up to 24-Bit Data
    • Figure 11. Format 2 or 3, Right-Justified 16-Bit or 24-Bit Data (Serial Control Port Mode Only)
  • Switching Characteristics - Software Mode - I·C Format
    • Figure 12. Software Mode Timing - I·C Format
  • Switching Characteristics - Software Mode - SPI Format
    • Figure 13. SPI Control Port Timing
• 5. Applications
  • 5.1 Stand-Alone Mode
    • 5.1.1 Access to Stand-Alone Mode
      • Table 2. Approximate Delay Time from Release of RST to Entering Standalone Mode
    • 5.1.2 Access to Master/Slave Mode
    • 5.1.3 System Clocking
      • Table 3. Speed Modes
    • 5.1.4 Clock Ratio Selection
      • Table 4. Clock Ratios - Stand-Alone Mode
    • 5.1.5 Interpolation Filter
    • 5.1.6 High-Pass Filter
    • 5.1.7 Mode Selection & De-Emphasis
      • Table 5. CS4270 Stand-Alone Mode Control
    • 5.1.8 Access to Serial Audio Interface Format
  • 5.2 Serial Control Port Mode
    • 5.2.1 Access to Serial Control Port Mode
    • 5.2.2 Access to Master/Slave Mode
    • 5.2.3 System Clocking
      • Table 6. Speed Modes
    • 5.2.4 Clock Ratio Selection
      • Table 7. Clock Ratios - Serial Control Port Mode
    • 5.2.5 Internal Digital Loopback
    • 5.2.6 Auto-Mute
    • 5.2.7 DC Offset Calibration Using the High-Pass Filter
    • 5.2.8 Oversampling Modes
  • 5.3 Popguard Transient Control
    • 5.3.1 Power-Up
    • 5.3.2 Power-Down
    • 5.3.3 Discharge Time
  • 5.4 De-Emphasis Filter (Single-Speed Mode Only)
    • Figure 14. De-Emphasis Curve
  • 5.5 Analog Connections
    • 5.5.1 Input Component Values
      • Table 8. Analog Input Design Parameters
      • Figure 15. CS4270 Example Analog Input Network
      • Figure 16. A/D THD+N Performance vs. Input Source Impedance
      • Figure 17. A/D Dynamic Range vs. Input Source Impedance
    • 5.5.2 Output Connections
      • Figure 18. CS4270 Recommended Analog Output Filter
  • 5.6 Mute Control
    • Figure 19. Suggested Active-Low Mute Circuit
  • 5.7 Synchronization of Multiple Devices
  • 5.8 Grounding and Power Supply Decoupling
• 6. Software Mode
  • 6.1 Software Mode - I·C Control Port
    • Figure 20. Software Mode Timing, I·C Write
    • Figure 21. Software Mode Timing, I·C Read
  • 6.2 Software Mode - SPI Control Port
    • 6.2.1 SPI Write
    • 6.2.2 SPI Read
      • Figure 22. Software Mode Timing, SPI Mode
    • 6.2.3 Memory Address Pointer (MAP)
• 7. Register Quick Reference
• 8. Register Description
  • 8.1 Device ID - Address 01h
  • 8.2 Power Control - Address 02h
    • 8.2.1 Freeze (Bit 7)
    • 8.2.2 PDN_ADC (Bit 5)
    • 8.2.3 PDN_DAC (Bit 1)
    • 8.2.4 Power Down (Bit 0)
  • 8.3 Mode Control - Address 03h
    • 8.3.1 ADC Functional Mode & Master/Slave Mode (Bits 5:4)
      • Table 9. Functional Mode Selection
    • 8.3.2 Ratio Select (Bits 3:1)
      • Table 10. MCLK Divider Configuration
    • 8.3.3 Popguard Transient Control (Bit 0)
  • 8.4 ADC and DAC Control - Address 04h
    • 8.4.1 ADC High Pass Filter Freeze for CH A (Bit 7)
    • 8.4.2 ADC High Pass Filter Freeze for CH B (Bit 6)
    • 8.4.3 Digital Loopback (Bit 5)
    • 8.4.4 DAC Digital Interface Format (Bits 4:3)
      • Table 11. DAC Digital Interface Formats
    • 8.4.5 ADC Digital Interface Format (Bit 0)
      • Table 12. ADC Digital Interface Formats
  • 8.5 Transition Control - Address 05h
    • 8.5.1 DAC Single Volume (Bit 7)
    • 8.5.2 Soft Ramp and Zero Cross Enable (Bits 6:5)
      • Table 13. Soft Cross or Zero Cross Mode Selection
    • 8.5.3 Invert Signal Polarity (Bits 4:1)
    • 8.5.4 De-Emphasis Control (Bit 0)
  • 8.6 Mute Control - Address 06h
    • 8.6.1 Auto-Mute (Bit 5)
    • 8.6.2 ADC Channel A & B Mute (Bits 4:3)
    • 8.6.3 Mute Polarity (Bit 2)
    • 8.6.4 DAC Channel A & B Mute (Bits 1:0)
  • 8.7 DAC Channel A Volume Control - Address 07h
  • 8.8 DAC Channel B Volume Control - Address 08h
    • Table 14. Digital Volume Control
• 9. Filter Plots
  • Figure 23. DAC Single-Speed Stopband Rejection
  • Figure 24. DAC Single-Speed Transition Band
  • Figure 25. DAC Single-Speed Transition Band (detail)
  • Figure 26. DAC Single-Speed Passband Ripple
  • Figure 27. DAC Double-Speed Stopband Rejection
  • Figure 28. DAC Double-Speed Transition Band
  • Figure 29. DAC Double-Speed Transition Band (detail)
  • Figure 30. DAC Double-Speed Passband Ripple
  • Figure 31. DAC Quad-Speed Stopband Rejection
  • Figure 32. DAC Quad-Speed Transition Band
  • Figure 33. DAC Quad-Speed Transition Band (detail)
  • Figure 34. DAC Quad-Speed Passband Ripple
  • Figure 35. ADC Single-Speed Stopband Rejection
  • Figure 36. ADC Single-Speed Stopband (detail)
  • Figure 37. ADC Single-Speed Transition Band (detail)
  • Figure 38. ADC Single-Speed Passband Ripple
  • Figure 39. ADC Double-Speed Stopband Rejection
  • Figure 40. ADC Double-Speed Stopband (detail)
  • Figure 41. ADC Double-Speed Transition Band (detail)
  • Figure 42. ADC Double-Speed Passband Ripple
  • Figure 43. ADC Quad-Speed Stopband Rejection
  • Figure 44. ADC Quad-Speed Stopband (detail)
  • Figure 45. ADC Quad-Speed Transition Band (detail)
  • Figure 46. ADC Quad-Speed Passband Ripple
• 10. Parameter Definitions
• 11. Package Dimensions
  • Thermal CharacteristicS
• 12. Ordering Information
• 13. Revision History