Cirrus Logic CDB4270 - Manual (Page 10)

10 DS686DB3
CDB4270
2.3 Internal Data Routing
Figure 4 shows the internal data routing topology between the CS4270, CS8416, CS8406 and the DSP
Header. Refer to the FPGA GUI Register Description section of this document for a description of the audio
data routing register settings.
.
C S 8 4 0 6
S D IN
C S 4 2 7 0 -F P G A -S D O U T
S D IO [1 :0 ]
C S 8 4 1 6 -F P G A -S D O U T
F P G A -S D IN
T X S D IO [1 :0 ]
C S 4 2 7 0
S D IN
S D O U T
D S P H e a d e r
S D IN
S D O U T
C S 8 4 1 6
S D O U T
F P G A -H D R -S D O U T
C S 4 2 7 0 -S D IN
C S 8 4 0 6 -S D IN
F P G A
D U T _ S D IO [1 :0 ]
Figure 4. Internal Data Routing