Cirrus Logic CDB4270 - Manual (Page 24)

24 DS686DB3
CDB4270
6. CDB4270 HARDWARE MODE SETTINGS
Schematic-Level Functional Description:
When the Flex GUI is not used and there is no serial port communication to the board, all devices are in HW Mode.
FPGA SW control is disabled in this condition, and DIP switches S1 and S2 on the CDB4270 set the FPGA Registers
to control board functionality. Note that the CS8406 and CS8416 are reset when SW/HW from the microprocessor
goes low (going from SW to HW Mode). See the schematic for switch name labels, and see
Table 13 .
Dip Switch
Logic State
b1, b0 nets
Functional Description
S1 0,0
As per Table 5 .
- CS4270 is Master
- CS8416 and CS8406 are Slaves to CS4270
- DSP Header Sub-clocks are Outputs from CS4270
S1 0,1
As per Table 5.
- CS8416 is Master
- CS4270 and CS8406 are Slaves to CS8416
- DSP Header Sub-clocks are Outputs from CS8416
S1 1,0
As per Table 5.
-DSP Header is Master
- CS4270, CS8416 and CS8406 are Slaves to DSP Header
- DSP Header Sub-clocks are Inputs
S1 1,1
As per Table 5.
- CS8406 is Master
- CS4270 and CS8416 are Slave to CS8406
- DSP Header Sub-clocks are Outputs from CS8406
Dip Switch
Logic State
b3, b2 nets
Functional Description
S1 0,0
As per Table 2 , Table 4 , Table 9.
CS4270 SDOUT to DSP Header SDOUT
CS4270 SDOUT to CS4270 SDIN
CS4270 SDOUT to CS8406 SDIN
S1 0,1
As per Table 2 , Table 4 , Table 9.
CS8416 SDOUT to DSP Header SDOUT
CS8416 SDOUT to CS4270 SDIN
CS8416 SDOUT to CS8406 SDIN
S1 1,0
As per Table 2 , Table 4 , Table 9.
DSP Header SDIN to DSP Header SDOUT
DSP Header SDIN to CS4270 SDIN
DSP Header SDIN to CS8406 SDIN
S1 1,1
As per Table 2 , Table 4 , Table 9.
DSP Header SDIN to DSP Header SDOUT
DSP Header SDIN to CS4270 SDIN
DSP Header SDIN to CS8406 SDIN
Dip Switch
Logic State
b4 nets
FPGA Functional Description
S1 0
As per Table 3.
MCLK from DSP Header
S1 1
As per Table 3.
MCLK from Oscillator (through CS8416), MCLK to DSP Header
Table 13. CDB4270 Hardware Mode - Functional Description