Cirrus Logic CDB4270 - Manual (Page 12)

12 DS686DB3
CDB4270
2.5 External MCLK Control
Several sources for MCLK exist on the CDB4270. The crystal oscillator, Y1, will master the MCLK bus when
no S/PDIF signal is input to the CS8416 (refer to the CS8416 data sheet for details on OMCK operation).
When S/PDIF data is present at the CS8416 input, the CS8416 generates a master clock whenever its in-
ternal PLL is locked to the incoming S/PDIF stream.
The DSP Header can master the MCLK bus or be an observation point for MCLK depending upon the state
of the driver control signals from the FPGA.
Refer to the Register Description section of this document for a description of the MCLK routing control reg-
isters.
.
CS8416
CS8406
DSP Header
FPGA
RMCK
OMCK OSC
OMCK
MCLK
CS4270
MCLK
MCLK.FROM.HDR
MCLK.FROM.8416
MCLK
MCLK.TO.HDR
Figure 6. External MCLK Control