Cirrus Logic CDB4270 - Manual (Page 20)

20 DS686DB3
CDB4270
5.3 CS4270 CONTROL - ADDRESS 01H
5.3.1 SDOUT Routing to Header (Bits 7:6)
Default = 00
Function:
These bits control the routing of SDOUT from the CS8416, CS4270 and the Header SDIN to the Header
SDOUT.
Table 2 shows the available settings.
5.3.2 MCLK Source (Bit 4)
Default = 1
Function:
This bit selects the source of the CS4270 MCLK signal. Table 3 shows the available settings.
5.3.3 SDOUT Routing to DUT (Bits 3:2)
Default = 00
Function:
These bits control the routing of SDOUT from the CS8416, CS4270 and the Header SDIN to the CS4270.
Table 4 shows the available settings .
7 6 5 4 3 2 1 0
SDIO.1 SDIO.0 Reserved MCLK DUT_SDIO.1 DUT_SDIO.0 SUB_CK.1 SUB_CK.0
SDIO.1 SDIO.0 SDIN/SDOUT Routing
0 0 CS4270 SDOUT source to DSP Header SDOUT
0 1 CS8416 SDOUT source to DSP Header SDOUT
1 0 SDIN from DSP Header to DSP Header SDOUT
1 1 Connect GND to DSP Header SDOUT
Table 2. SDOUT Routing to Header
MCLK MCLK Source
0 MCLK from DSP Header
1 MCLK from Oscillator (through CS8416), MCLK to DSP Header
Table 3. MCLK Source
DUT_SDIO.1 DUT_SDIO.0 SDIN/SDOUT Routing
0 0 CS4270 SDOUT source to CS4270 SDIN
0 1 CS8416 SDOUT source to CS4270 SDIN
1 0 SDIN from DSP Header to CS4270 SDIN
1 1 Connect GND to CS4270 SDIN
Table 4. SDOUT Routing to DUT