Cirrus Logic CDB4270 - Manual (Page 4)

4 DS686DB3
CDB4270
Figure 53.96 kHz, Crosstalk ...................................................................................................................... 34
Figure 54.96 kHz, Impulse Response ....................................................................................................... 34
Figure 55.FFT (192 kHz, 0 dB) ................................................................................................................. 34
Figure 56.FFT (192 kHz, -60 dB) .............................................................................................................. 34
Figure 57.FFT (192 kHz, No Input) ........................................................................................................... 34
Figure 58.FFT (192 kHz Out-of-Band, No Input) ....................................................................................... 34
Figure 59.192 kHz, THD+N vs. Input Freq ................................................................................................ 35
Figure 60.192 kHz, THD+N vs. Level ....................................................................................................... 35
Figure 61.192 kHz, Fade-to-Noise Linearity ............................................................................................. 35
Figure 62.192 kHz, Frequency Response ................................................................................................. 35
Figure 63.192 kHz, Crosstalk .................................................................................................................... 35
Figure 64.192 kHz, Impulse Response ..................................................................................................... 35
Figure 65.Block Diagram ........................................................................................................................... 36
Figure 66.CS4270 ..................................................................................................................................... 37
Figure 67.Analog Input .............................................................................................................................. 38
Figure 68.Analog Output ........................................................................................................................... 39
Figure 69.CS8406 S/PDIF Transmitter ..................................................................................................... 40
Figure 70.CS8416 S/PDIF Receiver ......................................................................................................... 41
Figure 71.Buffers - Clock/Data Routing .................................................................................................... 42
Figure 72.FPGA ........................................................................................................................................ 43
Figure 73.USB/RS232 Microprocessor ..................................................................................................... 44
Figure 74.Power ........................................................................................................................................ 45
Figure 75.Silk Screen ................................................................................................................................ 46
Figure 76.Top-Side Layer ......................................................................................................................... 47
Figure 77.Bottom-Side Layer .................................................................................................................... 48
LIST OF TABLES
Table 1. Revision Number ......................................................................................................................... 19
Table 2. SDOUT Routing to Header ......................................................................................................... 20
Table 3. MCLK Source .............................................................................................................................. 20
Table 4. SDOUT Routing to DUT .............................................................................................................. 20
Table 5. Sub-Clock Routing ...................................................................................................................... 21
Table 6. CS8406 OMCLK Frequency ....................................................................................................... 21
Table 7. CS8406 Master/Slave ................................................................................................................. 22
Table 8. CS8406 SDIN Format ................................................................................................................. 22
Table 9. CS8406 SDIN Source ................................................................................................................. 22
Table 10. CS8416 RMCLK Frequency ...................................................................................................... 23
Table 11. CS8416 Master/Slave ............................................................................................................... 23
Table 12. CS8416 SDOUT Format ........................................................................................................... 23
Table 13. CDB4270 Hardware Mode - Functional Description ................................................................. 24
Table 14. Connectors and Switches ......................................................................................................... 26
Table 15. Jumpers and Indicators ............................................................................................................. 26