1 capacitor placement, Cs4354 – Cirrus Logic CS4354 User Manual
Page 19
DS895F2
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CS4354
shows the recommended power arrangements with VA and VL connected to clean supplies. It is strongly
recommended that a single ground plane be used with the GND pins connected to the common plane; this
is important because both pin 6 and pin 10 provide analog ground reference to the CS4354. Should it be
necessary to split the ground planes, the CS4354 should be placed entirely in the analog plane. In this con-
figuration, it is critical that the digital and analog ground planes be tied together with a low-impedance con-
nection, ideally a strip of copper on the printed circuit board, at a single point near the CS4354.
All signals, especially clocks, should be kept away from the FILT+ pin in order to avoid unwanted coupling
into the DAC.
4.10.1
Capacitor Placement
Decoupling capacitors should be placed as close to the device as possible, with the low-value ceramic
capacitor being the closest. To further minimize impedance, these capacitors should be located on the
same PCB layer as the device. See
for the voltage present across pin pairs.
This is useful for choosing appropriate capacitor voltage ratings and orientation if electrolytic capacitors
are used.
The CDB4354 evaluation board demonstrates the optimum layout and power supply arrangements.