Figure 1. external serial clock mode input timing, Figure 2. internal serial clock mode input timing, Figure 3. internal serial clock generation – Cirrus Logic CS4354 User Manual
Page 9: Cs4354
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DS895F2
9
CS4354
Figure 1. External Serial Clock Mode Input Timing
Figure 2. Internal Serial Clock Mode Input Timing
Figure 3. Internal Serial Clock Generation
sclkh
t
slrs
t
slrd
t
sdlrs
t
sdh
t
sclkl
t
SDIN
SCLK
LRCK
SDIN
*
LRCK
MCLK
t
mclkf
sclkr
t
sdh
t
sdlrs
t
INTERNAL
SCLK
sclkw
t
The SCLK pulses shown are internal to the CS4354.
SDIN
LRCK
MCLK
*INTERNAL SCLK
1
N
2
N
* The SCLK pulses shown are internal to the CS4354.
N equals MCLK divided by SCLK
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