Cirrus Logic CS4385A - Manual (Page 25)

DS837F2 25
CS4385A
4.3.4 OLM #4
OLM #4 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to
SCLK at 256 Fs. Eight channels of MSB first 24-bit PCM data are input on SDIN1.
4.3.5 TDM
The TDM serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave
to SCLK at 256 Fs. Data is received by the most significant bit first on the first SCLK after an LRCK tran-
sition and is valid on the rising edge of SCLK. LRCK identifies the start of a new frame and is equal to the
sample rate, Fs. LRCK is sampled as valid on the rising SCLK edge preceding the most significant bit of
the first data sample and must be held valid for one SCLK period. Each time slot is 32 bits wide, with the
valid data sample left-justified within the time slot with the remaining bits being zero-padded.
4.4 Oversampling Modes
The CS4385A operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the M4, M3 and M2 pins in Hardware Mode or by the FM bits in Software Mode. Single-
Speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed
Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode
supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
The auto-speed mode detect feature allows for the automatic selection of speed mode based on the incom-
ing sample rate. This allows the CS4385A to accept a wide range of sample rates with no external interven-
tion necessary. The auto-speed-mode detect feature is available in both Hardware and Software Mode.
LSB MSB
24 clks
128 clks
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB MSB
DAC_A1
24 clks 24 clks 24 clks 24 clks 24 clks
Left Channel Right Channel
128 clks
LRCK
SCLK
SDIN1
DAC_A2 DAC_A3 DAC_B1 DAC_B2 DAC_B3
LSB MSB
24 clks
DAC_A4
LSB MSB
24 clks
DAC_B4
Figure 17. Format 11 - One Line Mode 4
Figure 18. Format 3 - TDM Mode
DAC_B3
LRCK
SCLK
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB SDIN1
DAC_A1 DAC_B1 DAC_A3 DAC_A2
256 clks
32 clks 32 clks 32 clks 32 clks 32 clks
LSB MSB
DAC_A4
32 clks
LSB MSB
DAC_B2
32 clks
LSB MSB
DAC_B4
32 clks
LSB
LSB MSB zero
Data