Cirrus Logic CS4385A - Manual (Page 31)

DS837F2 31
CS4385A
4.12.2 Software Mode
1. Hold RST low until the power supply is stable and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in Section 4.1 . In this state, the registers are reset to the default
settings, FILT+ will remain low, and VQ will be connected to VA/2.
2. Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in
Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode).
3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1; then set the format
and mode control bits to the desired settings.
If more than the stated range of LRCK cycles passes before CPEN bit is written, the chip will enter
Hardware Mode and begin to operate with the M0-M4 as the mode settings. CPEN bit may be written
at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit cannot be
set in time, the SDINx pins should remain static low (this way no audio data can be converted
incorrectly by the Hardware Mode settings).
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.
4.13 Recommended Procedure for Switching Operational Modes
For systems demanding the absolute minimum in clicks and pops, it is recommended that the MUTE bits
be set prior to changing significant DAC functions (such as changing sample rates or clock sources). The
mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK cannot be met
during clock source changes.
While in Software Mode, the DIF bits ( Section 7.3.1 ) should only be changed when the power-down (PDN)
bit is set to ensure proper switching from one mode to another. While in Hardware Mode, the mode select
pins should only be changed while the device is in reset (RST pin low) to ensure proper switching from one
mode to another.