2 direct dsd conversion (dir_dsd), 3 static dsd detect (static_dsd), 4 invalid dsd detect (invalid_dsd) – Cirrus Logic CS4385A User Manual

Page 40: 5 dsd phase modulation mode select (dsd_pm_mode), 6 dsd phase modulation mode enable (dsd_pm_en), Cs4385a

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40

DS837F2

CS4385A

7.4.2

Direct DSD Conversion (DIR_DSD)

Function:

When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control func-
tions.

When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.
In this mode, the full-scale DSD and PCM levels will not be matched (see

Section 1

), the dynamic range

performance may be reduced, the volume control is inactive, and the 50 kHz low-pass filter is not available
(see

Section 1

for filter specifications).

7.4.3

Static DSD Detect (STATIC_DSD)

Function:

When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE
register.

When set to 0, this function is disabled.

7.4.4

Invalid DSD Detect (INVALID_DSD)

Function:

When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-
tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE
register.

When set to 0 (default), this function is disabled.

7.4.5

DSD Phase Modulation Mode Select (DSD_PM_MODE)

Function:

When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for Phase Modulation
Mode. (See

Figure 21 on page 28

)

When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for Phase Modulation Mode.

7.4.6

DSD Phase Modulation Mode Enable (DSD_PM_EN)

Function:

When set to 1, DSD phase modulation input mode is enabled, and the DSD_PM_MODE bit should be set
accordingly.

When set to 0 (default), this function is disabled (DSD normal mode).

1

0

0

128x oversampled DSD data with a 2x MCLK to DSD data rate

1

0

1

128x oversampled DSD data with a 3x MCLK to DSD data rate

1

1

0

128x oversampled DSD data with a 4x MCLK to DSD data rate

1

1

1

128x oversampled DSD data with a 6x MCLK to DSD data rate

DIF2

DIF1

DIFO

DESCRIPTION

Table 8. Digital Interface Formats - DSD Mode

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