Cirrus Logic CS4373A - Manual (Page 18)

CS4373A
18 DS699F2
4. POWER MODES
The CS4373A has four power modes. AC test
modes and DC test modes are operational
modes, while the power down and sleep
modes are non-operational, standby modes.
4.1 Power Down
If MCLK is stopped, an internal loss-of-clock
detection circuit automatically places the
CS4373A into power down. Power down is in-
dependent of the MODE and ATT pin settings,
and is automatically invoked after approxi-
mately 40
µ s without an incoming MCLK edge.
In power down the AC and DC test circuitry is
inactive and the analog outputs are high im-
pedance. When used with the CS5376A digital
filter, the CS4373A is powered down immedi-
ately after reset since MCLK is disabled by de-
fault.
4.2 Sleep Modes
With MCLK enabled, selecting either of the
sleep modes (MODE 0, 7) places the
CS4373A into a micropower sleep state. Fol-
lowing completion of the AC and DC system
self-tests, the CS4373A is typically set into
sleep mode for normal data acquisition. In
sleep mode the AC and DC test circuitry is in-
active and the analog outputs are high imped-
ance.
4.3 AC Test Modes
With MCLK and TDATA active, selecting an
AC test mode (MODE 1, 2, 3, 6) causes the
CS4373A to output AC waveforms on the en-
abled analog outputs. AC test modes use the
low-power
∆Σ circuitry in the CS4373A to cre-
ate precision differential or common mode an-
alog AC output signals from the encoded
digital test bit stream (TBS) input.
4.4 DC Test Modes
With MCLK active, selecting a DC test mode
(MODE 4, 5) causes the CS4373A to generate
precision DC voltages on the analog outputs.
DC test modes use switch-capacitor level-
shifting buffer circuitry in the CS4373A to cre-
ate differential or common mode DC analog
output voltages from the voltage reference in-
put.
POWER DOWN
MCLK = OFF
MODE = XXX
SLEEP MODES
MCLK = ON
MODE = 0, 7
AC TEST MODES
MCLK = ON
MODE = 1, 2, 3, 6
DC TEST MODES
MCLK = ON
MODE = 4, 5
Figure 7. Power Mode Diagram