Cirrus Logic CS4373A - Manual (Page 23)

CS4373A
DS699F2 23
surement events, thereby synchronizing ana-
log sampling across a measurement network.
The timing accuracy of the input SYNC signal
from measurement node to measurement
node must be +/- 1 MCLK to maximize
MSYNC analog sample synchronization accu-
racy.
The CS4373A MSYNC input is rising-edge
triggered and resets the internal MCLK
counter/divider to guarantee synchronous op-
eration with other system devices. While the
MSYNC signal synchronizes the internal oper-
ation of the CS4373A, by default, it does not
synchronize the phase of the encoded digital
test bit stream (TBS) sine wave unless en-
abled in the digital filter TBSCFG register.
6.4 GPIO Connections
The CS5376A controls 12 general-purpose in-
put output (GPIO) pins through the digital filter
GPCFG registers. These GPIO pins are typi-
cally assigned to operate the CS4373A mode
and attenuator pins, along with the
CS3301A / CS3302A amplifiers input mux and
gain pins. The gain and attenuation settings of
the CS3301A / CS3302A amplifiers and
CS4373A are identically decoded to allow full-
scale performance testing at all system gain
ranges with shared GAIN and ATT control sig-
nals.
If precise timing control of operational modes
is required (for example, switching between
DC modes for pulse generation), an external
controller should directly toggle the MODE
pins of the CS4373A to avoid the delay asso-
ciated with writing to the CS5376A digital filter
GPCFG registers.