4 scr latch-up, 5 dc-dc converters, 4 scr latch-up 9.5 dc-dc converters – Cirrus Logic CS4373A User Manual
Page 29: Cs4373a
CS4373A
DS699F2
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rejected as specified in the
table.
9.4 SCR Latch-up
The VA- pin is tied to the CS4373A CMOS
substrate and must always be the most-nega-
tive voltage applied to the device to ensure
SCR latch-up does not occur. In general,
latch-up may occur when any pin voltage ex-
ceeds the limits of the
It is recommended to connect the VA- power
supply to system ground (GND) with a re-
verse-biased Schottky diode. At power up, if
the VA+ power supply ramps before the VA-
supply is established, the VA- pin voltage
could be pulled above ground potential
through the CS4373A device. If the VA- supply
is pulled 0.7 V or more above GND, SCR
latch-up can occur. A reverse-biased Schottky
diode will clamp the VA- voltage a maximum of
0.3 V above ground to ensure SCR latch-up
does not occur at power up.
9.5 DC-DC Converters
Many low-frequency measurement systems
are battery powered and utilize DC-DC con-
verters to efficiently generate power supply
voltages. To minimize interference effects, op-
erate the DC-DC converter at a frequency
which is rejected by the digital filter, or operate
it synchronous to the MCLK rate.
A synchronous DC-DC converter whose oper-
ating frequency is derived from MCLK will the-
oretically minimize the potential for “beat
frequencies” to appear in the
measurement
bandwidth. However this requires the source
clock to remain jitter-free within the DC-DC
converter circuitry. If clock jitter can occur with-
in the DC-DC converter (as in a PLL-based ar-
chitecture), it’s better to use a non-
synchronous DC-DC converter whose switch-
ing frequency is rejected by the digital filter.
During PCB layout, do not place high-current
DC-DC converters near sensitive analog com-
ponents. Carefully routing a separate DC-DC
“star” ground will help isolate noisy switching
currents away from the sensitive analog com-
ponents.