Cirrus Logic CS43L21 - Manual (Page 17)

DS723F1 17
CS43L21
10. After powering up the CS43L21, RESET should be held low after the power supplies and clocks are
settled.
11. See “Example System Clock Frequencies” on page 58 for typical MCLK frequencies.
12. See “Master” on page 29 .
13. “MCLK” refers to the external master clock applied.
Master Mode (Note 12)
Output Sample Rate (LRCK) All Speed Modes
(Note 13)
F
s
- Hz
LRCK Duty Cycle 45 55 %
SCLK Frequency 1/t
P
- 64•F
s
Hz
SCLK Duty Cycle 45 55 %
LRCK Edge to SDIN MSB Rising Edge t
d(MSB)
52 ns
SDIN Setup Time Before SCLK Rising Edge t
s(SD-SK)
20 - ns
SDIN Hold Time After SCLK Rising Edge t
h
20 - ns
Parameters Symbol Min Max Units
MCLK
128
-----------------
//
//
//
//
//
//
t
s(SD-SK)
MSB MSB-1
LRCK
SCLK
SDIN
t
s(LK-SK)
t
P
t
h
Figure 4. Serial Audio Interface Slave Mode Timing
//
//
//
//
//
//
t
s(SD-SK)
MSB MSB-1
LRCK
SCLK
SDIN
t
d(MSB)
t
P
t
h
Figure 5. Serial Audio Interface Master Mode Timing