Cirrus Logic CS43L21 - Manual (Page 40)

40 DS723F1
CS43L21
6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is listed in each bit description.
All “Reserved” registers must maintain their default state.
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
Chip I.D. (Chip_ID[4:0])
Default: 11011
Function:
I.D. code for the CS43L21. Permanently set to 11011.
Chip Revision (Rev_ID[2:0])
Default: 001
Function:
CS43L21 revision level. Revision B is coded as 001. Revision A is coded as 000.
6.2 Power Control 1 (Address 02h)
Notes:
1. To activate the power-down sequence for individual channels (A or B,) both channels must first be pow-
ered down either by enabling the PDN bit or by enabling the power-down bits for both channels. En-
abling the power-down bit on an individual channel basis after the D/A has fully powered up will mute
the selected channel without achieving any power savings.
2. Reserved bits 1 - 4 should always be set “high” by the user to minimize power consumption during nor-
mal operation.
Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the se-
lect channels, 3.) disable the PDN bit.
Power Down DAC X (PDN_DACX)
Default: 0
0 - Disable
1 - Enable
Function:
DAC channel x will either enter a power-down or muted state when this bit is enabled. See above.
Power Down (PDN)
Default: 0
0 - Disable
1 - Enable
7 6 5 4 3 2 1 0
Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0
7 6 5 4 3 2 1 0
Reserved PDN_DACB PDN_DACA Reserved Reserved Reserved Reserved PDN