Cirrus Logic CS43L21 - Manual (Page 32)

32 DS723F1
CS43L21
4.8 Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the device in standby,
1. Mute the DACs.
2. Disable soft ramp and zero cross volume transitions.
3. Set the PDN bit to 1.
4. Wait at least 100 µs.
The DAC will be fully powered down after this 100 µs delay. Prior to the removal of the master clock
(MCLK), this delay of at least 100 µs must be implemented after step
3 to avoid premature disruption
of the device’s power down sequence.
A disruption in the DAC’s power down sequence (i.e. removing the MCLK signal before this 100 µs de-
lay) has consequences on the headphone amplifier: The charge pump may stop abruptly, causing the
headphone amplifiers to drive the outputs up to the +VA_HP supply.
The disruption of the DAC’s power down sequence may also cause clicks and pops on the output of the
DAC’s as the modulator holds the last output level before the MCLK signal was removed.
5. Optionally, MCLK may be removed at this time.
6. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be
reset to their default state.
7. Power Supply Removal (Option 1): Switch power supplies to a high impedance state.
8. Power Supply Removal (Option 2): To minimize pops when the power supplies are pulled to ground, a
discharge resistor must be added in parallel with the capacitor on the FILT+ pin. With a 1 M
 resistor
and a 2.2 µF capacitor on FILT+, FILT+ will ramp to ground in approximately 5 seconds. A 1 M
 resistor
on FILT+ reduces the full scale input/output voltage by approximately 0.25 dB.
After step 5 , wait the required time for FILT+ to ramp to ground before pulling VA to ground.