Cirrus Logic CS43L21 - Manual (Page 33)

DS723F1 33
CS43L21
Initialization
Software Mode
Registers setup to
desired settings.
RESET = Low?
No Power
1. No audio signal
generated.
Off Mode (Power Applied)
1. No audio signal generated.
2. Control Port Registers reset
to default.
Control Port
Active
Control Port Valid
Write Seq. within
10 ms?
Hardware Mode
Minimal feature
set support.
PDN bit = '1'b?
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Valid
MCLK/LRCK
Ratio?
No
Yes No
Yes
No
Yes
Yes
No
Normal Operation
Audio signal generated per control port or stand-
alone settings.
Analog Output Freeze
1. Aout bias = last audio sample.
2. DAC Modulators stop operation.
3. Audible pops.
ERROR: MCLK removed
PDN bit set to '1'b
(software mode only)
Standby Mode
1. No audio signal generated.
2. Control Port Registers retain
settings.
Reset Transition
1. Pops suppressed.
Power Off Transition
1. Audible pops.
ERROR: Power removed
Valid
MCLK Applied?
No
20 ms delay
Charge Caps
1. VQ Charged to
quiescent voltage.
2. Filtx+ Charged.
Digital/Analog
Output Muted
50 ms delay
Charge Pump
Powered Up
Headphone Amp
Powered Up
20 s delay
Headphone Amp
Powered Down
20 s delay
Stand-By
Transition
1. Pops suppressed.
ERROR: MCLK/LRCK ratio change
RESET = Low
Figure 17. Initialization Flow Chart