Cirrus Logic CS43L21 - Manual (Page 53)

DS723F1 53
CS43L21
Limiter RELEASE Rate (RRATE[5:0])
Default: 111111
Function:
Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in
the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting.
The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
6.16 Limiter Attack Rate Register (Address 1Bh)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Limiter Attack Rate (ARATE[5:0])
Default: 000000
Function:
Sets the rate at which the limiter attenuates the analog output from levels above the maximum setting in the
limiter threshold register.
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
6.17 Status (Address 20h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A ”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: 0
Function:
Indicates an invalid MCLK to LRCK ratio. See “Serial Port Clocking” section on page 28“Serial Port Clock-
ing” on page 28 for valid clock ratios.
Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
Binary Code Release Time
000000 Fastest Release
··· ···
111111 Slowest Release
7 6 5 4 3 2 1 0
Reserved Reserved ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0
Binary Code Attack Time
000000 Fastest Attack
··· ···
111111 Slowest Attack
7 6 5 4 3 2 1 0
Reserved SP_CLKERR SPEA_OVFL SPEB_OVFL PCMA_OVFL PCMB_OVFL Reserved Reserved