Cirrus Logic CS43L21 - Manual (Page 21)

DS723F1 21
CS43L21
POWER CONSUMPTION
See (Note 20)
20. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =
48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and mas-
ter/slave operation.
21. RESET pin 25 held LO, all clocks and data lines are held LO.
22. RESET pin 25 held HI, all clocks and data lines are held HI.
23. VL current will slightly increase in master mode.
Power Control Registers Typical Current (mA)
Operation
02h 03h
PDN_DAC
B
PDN_DAC
A
BIT 4 BIT 3 BIT 2 BIT 1 PDN BIT 3 BIT 2 BIT 1 V
i
VA_HP
i
VA
i
VD
i
VL
(Note
23)
Total
Power
(mW
rms
)
1 Off (Note 21)
x x x x x x x x x x 1.8 0 0 0 0 0
2.5 0 0 0 0 0
2 Standby (Note 22)
x x x x x x 1 x x x 1.8 0 0.01 0.02 0 0.05
2.5 0 0.01 0.03 0 0.10
5 Mono Playback 1 0 1 1 1 1 0 1 1 1 1.8 1.66 1.40 2.35 0.01 9.74
2.5 2.03 1.71 3.48 0.02 18.08
6 Stereo Playback
0 0 1 1 1 1 0 1 1 1 1.8 2.77 2.05 2.35 0.01 12.93
2.5 3.21 2.50 3.49 0.02 23.02