Cirrus Logic CS5378 - Manual (Page 21)

CS5378
DS639F3 21
5. RESET CONTROL
The CS5378 reset signal is active low. When re-
leased, a series of self-tests are performed and the
device either actively boots from an external EE-
PROM or enters an idle state waiting for microcon-
troller configuration.
5.1 Pin Descriptions
RESET - Pin 18
Reset input, active low.
GPIO7:BOOT - Pin 28
Boot mode select, latched immediately following
reset. Weak (~100 k
Ω) internal pull-up defaults
high, external 10 k
Ω pull-down required to set low.
5.2 Reset Self-Tests
After RESET is released but before booting, a se-
ries of digital filter self-tests are run. Results are
combined into the SELFTEST register (0x2F),
with 0x0AAAAA indicating all passed. Self-tests
require 60 ms to complete.
5.3 Boot Configurations
The logic state of the BOOT pin after reset deter-
mines if the CS5378 actively reads configuration
information from EEPROM or enters an idle state
waiting for a microcontroller to write configuration
commands.
EEPROM Boot
When the BOOT pin is high after reset, the CS5378
actively reads data from an external serial EE-
PROM and then begins operation in the specified
configuration. Configuration commands and data
are encoded in the EEPROM as specified in the
‘Configuration By EEPROM’ section of this data
sheet, starting on page 25.
Microcontroller Boot
When the BOOT pin is low after reset, the CS5378
enters an idle state waiting for a microcontroller to
write configuration commands and initialize filter
operation. Configuration commands and data are
written as specified in the ‘Configuration By Mi-
crocontroller’ section of this data sheet, starting on
page 30.
RESET
Self-Tests
SELFTEST
Register
BOOT
Pin
EEPROM
Boot
μController
Boot
1
0
Figure 11. Reset Control Block Diagram
BOOT Reset Mode
1 EEPROM boot
0 Microcontroller boot
Self-Test
Type
Pass
Code
Fail
Code
Program ROM 0x00000A 0x00000F
Data ROM 0x0000A0 0x0000F0
Program RAM 0x000A00 0x000F00
Data RAM 0x00A000 0x00F000
Execution Unit 0x0A0000 0x0F0000