Cirrus Logic CS5378 - Manual (Page 61)

CS5378
DS639F3 61
Data Delay - DDLY[5:0]
Programs full period delays for TBSDATA, up to a
maximum of 63 bits.
Gain - TBSGAIN[23:0]
Scales the amplitude of the sine wave output. Max-
imum 0x04FFFF, nominal 0x04B000.
17.4 TBS Data Source
An on-chip 24-bit 1024 point digital sine wave is
stored on the CS5378 which will produce the test
signal frequencies listed in Table 18. Additional
discrete test frequencies and output rates can be
programmed by varying the interpolation factor
and output rate.
17.5 TBS Sine Wave Output
The TBS generator uses data from digital filter
memory to create a sine wave test signal that can
drive a test DAC. Sine wave frequency and output
data rate are calculated as shown by the character-
istic equation of Table 18.
The sine wave maximum
ΔΣ one’s density output
from the TBS generator is set by the TBSGAIN
register. TBSGAIN can be programmed up to a
maximum of 0x04FFFF, with the TBS generator
unstable for higher amplitudes. For the CS5373A
test DAC, a gain value of 0x04B000 produces an
approximately full scale sine wave output (5 V
pp
differential).
Test Bit Stream Characteristic Equation:
(Signal Freq) * (# TBS Data) * (Interpolation + 1) = Output Rate
Example: (31.25 Hz) * (1024) * (0x07 + 1) = 256 kHz
Signal
Frequency
(TBSDATA)
Output
Rate
(TBSCLK)
Output Rate
Selection
(RATE)
Interpolation
Selection
(INTP)
10.00 Hz 256 kHz 0x4 0x18
10.00 Hz 512 kHz 0x5 0x31
25.00 Hz 256 kHz 0x4 0x09
25.00 Hz 512 kHz 0x5 0x13
31.25 Hz 256 kHz 0x4 0x07
31.25 Hz 512 kHz 0x5 0x0F
50.00 Hz 256 kHz 0x4 0x04
50.00 Hz 512 kHz 0x5 0x09
125.00 Hz 256 kHz 0x4 0x01
125.00 Hz 512 kHz 0x5 0x03
Table 18. TBS Configurations Using On-chip Data