Cirrus Logic CS5378 - Manual (Page 23)

CS5378
DS639F3 23
6.4 Master Clock Jitter and Skew
Care must be taken to minimize jitter and skew on
the distributed system clock as both parameters af-
fect measurement performance.
Jitter on the input clock causes jitter in the generat-
ed modulator clock, resulting in sample timing er-
rors and increased noise.
Skew between input clocks from node to node cre-
ates a sample timing offset, resulting in systematic
measurement errors in a reconstructed signal.