Cirrus Logic CS5378 - Manual (Page 7)

CS5378
DS639F3 7
DC offset.
- Calibration engine for automatic calcula-
tion of offset correction factor.
1.2 Integrated Peripheral Features
• Low jitter PLL to generate local clocks.
- 1.024 MHz, 2.048 MHz, 4.096 MHz stan-
dard clock or Manchester encoded input.
• Synchronous operation for simultaneous sam-
pling in multi-sensor systems.
- MCLK / MSYNC output signals to syn-
chronize external components.
• High speed serial data output.
- Asynchronous operation to 4 MHz for di-
rect connection to system telemetry.
- Internal 8-deep data FIFO for flexible out-
put timing.
- Selectable 24-bit data only or 32-bit sta-
tus+data output.
• Digital test bit stream signal generator suitable
for CS5373A
ΔΣ test DAC.
- Sine wave output mode for testing total har-
monic distortion.
• Time break controller to record system timing
information.
- Dedicated TB status bit in the output data
stream.
- Programmable output delay to match sys-
tem group delay.
• 8 General Purpose I/O (GPIO) pins for local
hardware control.
1.3 System Level Features
• Flexible configuration options.
- Configuration 'on-the-fly' via microcon-
troller or system telemetry.
- Fixed configuration via stand-alone boot
EEPROM.
• Low power consumption.
- 16 mW at 500 SPS OWR.
- 100
μW standby mode.
• Flexible power supply configurations.
- Separate digital logic core, telemetry I/O,
and PLL power supplies.
- Telemetry I/O and PLL interfaces operate
Figure 2. Digital Filtering Stages
Sinc Filter
2 - 64000
FIR1
4
FIR2
2
IIR1 IIR2
1
st
Order 2
nd
Order
Output to High Speed Serial Interface
DC Offset
Corrections
Output Word Rate from 4000 SPS ~ 1 SPS
Gain &
Modulator
512 kHz
Input