Cirrus Logic CS5480 - Manual (Page 18)

CS5480
18 DS980F3
4.4 Phase Compensation
Phase compensation changes the phase of voltage
relative to current by adding a delay in the decimation
filters. The amount of phase shift is set by the PC
register bits CPCCx[1:0] and FPCCx[8:0] for current
channels. For voltage channels, only bits CPCCx[1:0]
affect the delay.
Fine phase compensation control bits, FPCCx[8:0],
provide up to 1/OWR delay in the current channels.
Coarse phase compensation control bits, CPCCx[1:0],
provide an additional 1/OWR delay in the current
channel or up to 2/OWR delay in the voltage channel.
Negative delay in voltage channel can be implemented
by setting a longer delay in the current channel than the
voltage channel. For a OWR of 4000Hz, the delay range
is ±500µs, a phase shift of ±8.99° at 50Hz and ±10.79°
at 60Hz. The step size is 0.008789° at 50Hz and
0.010547° at 60Hz.
4.5 DC Offset and Gain Correction
The system and CS5480 inherently have component
tolerances and gain and offset errors, which can be
removed using the gain and offset registers. Each
measurement channel has its own set of gain and offset
registers. For every instantaneous voltage and current
sample, the offset and gain values are used to correct
DC offset and gain errors in the channel (see section
7.
System Calibration on page 63 for more details).
4.6 High-pass and Phase Matching Filters
Optional high-pass filters (HPF in Figures 9 and 10 )
remove any DC component from the selected signal
paths. Each power calculation contains a current and
voltage channel. If an HPF is enabled in only one
channel, a phase matching filter (PMF) should be
applied to the other channel to match the phase
response of the HPF. For AC power measurement,
high-pass filters should be enabled on the voltage and
current channels. For information about how to enable
and disable the HPF or PMF on each channel, refer to
section
6.6.3 Configuration 2 (Config2) – Page 16,
Address 0 on page 40.
4.7 Digital Integrators
Optional digital integrators (INT in Figures 9 and 10 ) are
implemented on both current channels (I1, I2) to
compensate for the 90º phase shift and 20dB/decade
gain generated by the Rogowski coil current sensor.
When a Rogowski coil is used as the current sensor, the
integrator (INT) should be enabled on that current
channel. For information about how to enable and
disable the INT on each current channel, refer to section
6.6.3 Configuration 2 (Config2) – Page 16, Address 0 on
page 40.
4.8 Low-rate Calculations
All the RMS and power results come from low-rate cal-
culations by averaging the output word rate (OWR) in-
stantaneous values over N samples where N is the
value stored in the SampleCount register. The low-rate
interval or averaging period is N divided by OWR
(4000Hz if MCLK = 4.096MHz). The CS5480 provides
two averaging modes for low-rate calculations: Fixed
Number of Samples Averaging mode and Line-cycle
Synchronized Averaging mode. By default, the CS5480
averages with the Fixed Number of Samples Averaging
mode. By setting the AVG_MODE bit in the Config2 reg-
ister, the CS5480 will use the Line-cycle Synchronized
Averaging mode.
 N ÷
N 
N ÷
N 
N ÷
N 

N ÷
N 

Registers
MU
X
... ...
APCM
Config 2
V1(V2)
I1 (I2)
P1 (P2)
Q1 (Q2)
I1 ACOFF (I2 ACOFF )
S1 (S2)


PF1 (PF2)
X
I1
RMS
(I2
RMS
)
V1
RMS
(V2
RMS
)
Q1
AVG
(Q2
AVG
)
P1
AVG
(P2
AVG
)
-
+
Q1
OFF
(Q2
OFF
)

+
+
P1
OFF
(P2
OFF
)

+
+
X
X
+
+
Inverse
Figure 11. Low-rate Calculations