Cirrus Logic AN83 - Manual (Page 10)

AN83
10 AN83REV3
When the MC68302 generates address 0D00300h,
the address seen by the CS8900A will be 00300h
with one of the IO commands (IOR or IOW) active.
Similarly when the MC68302 generates address
0D01400h, the address seen by the CS8900A will
be 01400h with one of its memory commands
(MEMR or MEMW) active. For a MC68302, you
can also specify the number of wait states that
should be inserted automatically when address
space assigned to CS1 is accessed. The number of
wait states used depends upon the clock input to the
MC68302. Please do a complete timing analysis
before defining wait states.
Read and Write Signals
The combination of OR gates and an inverter
shown in Figure 3, generates IO commands (IOR,
IOW) as well as memory commands (MEMR,
MEMW) for the CS8900A. Since the CS1 gates
these signals, the IO or memory commands are not
generated unless the address on the address bus is
stable. Further, for an access in memory mode, an
IO command is not active.
SBHE Signal
The CS8900A is a 16 bit device and it should be
used as a 16 bit device. However, after a hardware
or software reset, the CS8900A behaves as an 8 bit
device. Any transition on pin SBHE places the
CS8900A into 16-bit mode. Further, for a 16-bit
access, the SBHE pin of the CS8900A must be low.
In the design example, the CPU address line A0 is
connected to SBHE. Before any access to the
CS8900A, the design must guarantee one transition
on SBHE pin.
Other Control Signals
All other control signals can be tied HIGH or
LOW. The signal REFRESH, TEST, SLEEP,
AEN should be tied inactive.
74F32
74F32
74F32
74F32
74F04
74F04
CS1*
R/W*
SBHE*
SA0
SA [1:11]
SA12
SA[13:19]
MEMW*
IOW*
MEMR*
IOR*
INTRQ0
UDS*/A0
A[1:11]
A12
CS1*
R/W*
INT*
CS8900
MC68302
Interrupt
Controller
Figure 3. Connection of CS8900A to MC68302