Figure 9. overall schematic, An83 – Cirrus Logic AN83 User Manual
Page 19
AN83
AN83REV3
19
SA00
SA01
SA02
SA03
SA04
SA05
SA06
SA07
SA08
SA09
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
ISA0
ISA1
ISA2
ISA3
ISA4
ISA5
ISA6
ISA7
ISA8
ISA9
ISA10
ISA11
ISA12
ISA13
ISA14
ISA15
ISA16
ISA17
ISA18
ISA19
37
38
39
40
41
42
43
44
45
46
47
48
50
51
52
53
54
58
59
60
CHIPSEL
MEMW
MEMR
IOW
IOR
REFRESH
SBHE
AEN
7
28
29
62
61
49
36
63
SMEMW
SMEMR
IOW
IOR
REFRESH
SBHE
AEN
76
77
75
TSTSEL
RESET
TESTSEL
SLEEP
RESET
+5V
XTAL
20.0 MHz
X1
1
2
97
98
93
XTL1
XTL2
RES
R4
4.99k, 1%
EL
C
S
DV
S
S
3
A
DV
S
S
1
A
DVSS4
D
V
DD4
DVSS3
D
V
DD3
DVSS2
D
V
DD2
DVSS1
D
V
DD1
AV
S
S
3
AVDD3
AV
S
S
2
AVDD2
AV
S
S
1
AVDD1
AV
S
S
4
AV
S
S
0
EEDA
TAI
N
EESK
2
57
10
70
69
55
56
23
22
8
9
94
95
86
85
89
90
96
1
6
4
C1
2
C1
4
C1
3
C9
C8
C1
1
C1
0
0.
1
µ
F
+5V
EE_CLK
+5V
0.1
µ
F
C7
1
2
3
5
8
4
7
6
VCC
D0
NC2
NC1
1K_EEPROM_S
CS
CLK
D1
VSS
U3
EECS
EEDATAOUT
3
5
12
U1
CS8900
RXD+
TXD-
TXD+
INTRQ0
INTRQ1
INTRQ2
INTRQ3
MEMCS16
I0CS16
I0CHRDY
DMARQ0
DMARQ1
DMARQ2
CSOUT
91
88
87
32
31
30
35
34
33
64
15
13
11
17
10BT_RD+
10BT_TD-
10BT_TD+
IRQ10
IRQ11
IRQ12
IRQ5
MEMCS16
I0CS16
I0CHRDY
DRQ5
DRQ6
DRQ7
IS
A
_
D
0
IS
A
_
D
1
IS
A
_
D
2
IS
A
_
D
3
IS
A
_
D
4
IS
A
_
D
5
IS
A
_
D
6
IS
A
_
D
7
IS
A
_
D
8
IS
A
_
D
9
IS
A
_
D
1
0
IS
A
_
D
1
1
IS
A
_
D
1
2
IS
A
_
D
1
3
IS
A
_
D
1
4
IS
A
_
D
1
5
65 66
67 68 71
72 73 74 27
26 25 24 21
20 19 18
SD
0
SD
1
SD
2
SD
3
SD
4
SD
5
SD
6
SD
7
SD
8
SD
9
SD
1
0
SD
1
1
SD
1
2
SD
1
3
SD
1
4
SD
1
5
DM
A
C
K0
DM
A
C
K2
DM
A
C
K3
16 14 12
DAC
K
5
DAC
K
6
DAC
K
7
80
79
82
81
84
83
78
100
99
RXD- 92
10BT_RD-
DI-
DI+
CI-
CI+
DO-
DO+
BSTATUS / HC1
LED2
LED0/HC0
0.
1
µ
F
0.
1
µ
F
0.
1
µ
F
0.
1
µ
F
0.
1
µ
F
0.
1
µ
F
Figure 9. Overall Schematic