Cirrus Logic AN83 - Manual (Page 11)

AN83
AN83REV3 11
Status Signals from CS8900A
There are several status signals that are output from
the CS8900A, such as IOCHRDY, IOCS16,
MCS16, etc. In the most embedded designs, they
are not needed. Those pins from the CS8900A
should be left open.
Databus (SD[0:15]) Connection
All the internal registers of the CS8900A are 16 bit
wide. For all the registers, bit F of the register is ac-
cess via SD15 and bit 0 of register is accessed via
SD0.
To be compatible with byte ordering with ISA bus,
the CS8900A provides the bytes received from the
Ethernet wire in the following fashion. Assume
that the data received from the Ethernet wire is 01,
02, 03, 04, 05, ... where the 01 is the first byte, 02
is the second byte and so on. When the CS8900A
transfers that data to the host CPU, the data words
are read from the CS8900A as 0201, 0403, etc. For
certain microprocessor systems, the designer may
prefer to read the data as 0102, 0304, etc. In such
a case, the databus connections to the CS8900A
can be altered by connecting the CPU databus
D[0:7] to the SD[8:15] pins of the CS8900A and
the CPU databus D[8:15] to the SD[0:7] pins of the
CS8900A. In such a case, make sure that all the
register and bit definitions in the CS8900A are also
byte swapped. Information that is normally appears
at bits [0:7] will now appear on bits [8:15], and in-
formation that usually appears on bits [8:15] will
now appear on bits [0:7].
Checklist for Signal Connections to the
CS8900A
Please refer to the datasheet for the CS8900A for
the pin assignment and pin descriptions of various
signals discussed in this section.
Clock: There are two options for the clock connec-
tion to the CS8900A. You may connect a 20.000
MHz crystal between XTL1 (pin 97) and XTL2
(pin 98) pins of the CS8900A. Or, if there a 20
MHz clock available in the system, it can be con-
nected to the XTL1 (pin 97) pin of the CS8900A.
It is important that this clock be TTL or CMOS
with 40/60 duty cycle and ±50 ppm accuracy.
SBHE signal: It is recommended that the
CS8900A be used in 16-bit mode. After a hard-
ware or software reset, the CS8900A comes up as
an 8-bit device. A transition on SBHE signal (pin
36) makes the CS8900A function as a 16-bit de-
vice. After this transition, the SBHE can be kept
low. For a 16-bit access of the CS8900A, the
SBHE and address line SA0 (pin 37) must be low.
Un-aligned word accesses to the CS8900A are not
supported. In a system, the SBHE line can be con-
nected to address line SA0. In such a case, after a
hardware or software reset, do a dummy read from
an odd address to provide transition on the SBHE
line. For memory mode, there is one more alterna-
tive for the SBHE connection. For a memory mode
operation, if a CHIPSEL pin is controlled by an ex-
ternal chip select, the CHIPSEL can be connected
to the SBHE. In this case, after a hardware and
software reset, do a dummy access to the CS8900A
and ignore data.
EEPROM Optional
The CS8900A has an interface for a serial EE-
PROM. Most of the networking applications use
this EEPROM to store IEEE MAC (Media Access
Control) address. Since the CS8900A supports 1 or
2 Kbits of EEPROM, the EEPROM is also used to
store information such as hardware configuration,
software driver configuration, etc. Any location in
the EEPROM can be read or written through the
CS8900A.
You will require EEPROM if the IO address for the
CS8900A has to be other then 0300h, or the only
mode supported by the CS8900A is memory mode.
For all other cases an EEPROM is optional. How-
ever, most of the software drivers supplied by Cir-
rus assume that there is an EEPROM connected to
the CS8900A or driver configuration data is stored