Cirrus Logic AN83 - Manual (Page 26)

AN83
26 AN83REV3
loaded at the Boot PROM base address register in-
dicates the starting location in host memory where
the Boot PROM is mapped. The Boot PROM ad-
dress mask indicates the size of the Boot PROM.
The lower 12 bits of the mask are ignored and
should be 000h. This limits the 434 Boot PROM
size to increments of 4K bytes. The CS8900A will
not generate an address decode for the Boot PROM
until the Boot PROM base address register and the
mask register are loaded. For example, say a 16K
Boot PROM is used and it is to be located starting
at address 0D0000h. Before this Boot PROM is
accessed, load the following registers with the val-
ues shown in Table 2.
The address mask that will be used by the
CS8900A is 0FC000h. The CS8900A will com-
pare SA[19:14] with the value 0D0h. Whenever
there is a match, it will assert the signal CSOUT to
generate an address decode for the Boot PROM. In
the reference design, the same signal is also used to
enable the data buffer, 74LS245, at location U7.
LEDs
A pair of LEDs are provided in the reference design
to indicate link OK and line active status. The pair
of LEDs are packaged one on the top of the other at
location LED1. The top LED is driven by the LIN-
KLED pin while the bottom LED is driven by the
LANLED pin of the CS8900A. The top LED lights
up when the CS8900A has the link pulse. The bot-
tom LED lights up when the CS8900A transmits or
receives a packet or senses a collision. The LEDs
are directly driven by the CS8900A. Two 680 Ohm
resistors limit the current flowing through the LED
circuitry.
10BASE-T Interface
The 10BASE-T interface for the CS8900A is
straight forward. Please refer to Figure 8 or 10 for
connections and components of this circuit. Trans-
mit and receive signal lines from the CS8900A are
connected to an isolation transformer at location
T3. For 5V operation this isolation transformer has
a 1:1 ratio between the primary and the secondary
windings on the receive side and 1:
√2 (1:1.41) ratio
between the primary and secondary windings for
the transmit lines. For 3.3V operation the receive
side is 1:1 and the transmit side is 1:2.5. Resistor
R2 provides termination for the receive lines. Re-
sistors R4 and R5 are in series with the differential
pair of transmit lines for impedance matching.
AUI Interface
Please refer to Figure 16 for connection of AUI sig-
nals to the CS8900A. The AUI lines from the 15-
pin sub-D connector (location J2) are connected to
the CS8900A through an isolation transformer at
T2. This isolation transformer has three windings
for three pairs of differential AUI signals: transmit,
receive and collision. All three windings have a
turns ratio of 1:1 between the primary and second-
ary windings. Circuitry consisting of R6, R7 and
C14 provides impedance termination for the colli-
sion differential pair. Circuitry consisting of R8,
R9 and C15 provides impedance termination for
the receive differential pair. The +12 volt power
going out to the AUI connector is safeguarded by
the fuse at F1. The AUI interface at J2 can be used
to connect external Media Access Units (MAU).
These MAUs allow the AUI interfaced to be used
to interface with 10BASE-5 or 10BASE-F.
Register Word
Offset
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Base +
Hex
value Description
30h 0000h Boot PROM Base address -
low word
32h 000Dh Boot PROM Base address -
high word
34h C000h Boot PROM address mask -
low word
36h 000Fh Boot PROM address mask -
high word
Table 2. BootPROM Descriptions Stored in CS8900A
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