Cirrus Logic AN83 - Manual (Page 32)

AN83
32 AN83REV3
face is used to generate the serial data stream on
EEDataOut pin (serial data out) with the EESK (se-
rial clock). Whenever ELSEL bit is set, ELCS pin
becomes active (LOW) instead of EECS pin during
the EEPROM operations. Since the EECS pin re-
mains inactive, the EEPROM that is interfaced to
the CS8900A is not enabled.
For the PAL in the design example, one should use
a “Program disable” EEPROM command. (Opcode
00000b). For example, if the CS8900A is to be
placed at PC memory space of 0A00000h, that
means the Q[23:20] should be 0Ah. To program
the 16R4, write 040Ah at Packet Page Base + 040h.
The instruction will take about 10 micro-seconds to
execute.
The electrical connections required to use external
logic are shown in Figure 21. At reset, the
CS8900A samples ELCS pin and if it is not
"LOW", it realizes presence of external address de-
code logic. The same reset signal also makes
ADD_VALID inactive, and thus prevents a signal
CHIPSEL_b from becoming active until Q[23:20]
are initialized. When a host CPU writes to Pack-
etPage base address + 040h to program values for
Q[23:20], the CS8900A then shifts that data serial-
ly in to the PAL or GAL. This makes
ADD_VALID signal active.
From this point onwards LA[23:20] are monitored
whenever ALE is active (HIGH). When the decode
logic finds a match, CHIPSEL_b signal is asserted.
This signal remains asserted until ALE becomes
active and the LA[23:20] do not match with
Q[23:20]. The internal decoder of the CS8900A is
active only when CHIPSEL_b is active (LOW).
1
11
2
3
4
5
6
7
8
9
CLK
G
10
11
12
13
14
15
16
17
I/00
I/01
I/02
I/03
12
13
18
19
14
15
16
17
00
01
02
03
CHIPSEL_B (CS8900 Pin7)
PAL16R4
ELCS
EEDOUT
BALE
LA23
LA22
LA21
LA20
RESET
EE_SK
(CS8900 Pin2)
CS8900 Pin5)
(ISA B28)
(ISA C02)
(ISA C03)
(ISA C04)
(ISA C05)
(ISA B02)
(CS8900 Pin 4)
Figure 21. PAL Decode of LA[20-23]
CS8900
Et
he
rnet
I
n
te
rf
ace
AU
I o
r
1
0
BA
SE-T
Te
rm
in
a
ti
n
g
Re
sisto
rs
Is
olat
ion T
ra
n
sf
o
rmer
or
Tr
an
sfo
rme
r w
ith CMC
C
onn
e
c
to
r
Figure 22. Typical CS8900A Ethernet Connection