Cirrus Logic AN83 - Manual (Page 49)

AN83
AN83REV3 49
IEEE Physical Address
The format of the 48-bit IEEE physical address as expected by the MAC driver is illustrated by the follow-
ing example. (Must be initialized by OEM before shipping adapter.)
Example physical address: 000102030405h
ISA Configuration Flags
The ISA Configuration Flags specify how the CS8900A will utilize ISA system resources.
Bit 15 Memory Mode Flag - Indicates the CS8900A will use shared memory for IO operations.
Refer to the CS8900A Data Sheet for a description of the shared memory interface. Default
is disabled.
Bit 14 Boot PROM Flag - Indicates a Boot PROM is installed. Refer to the CS8900A Data Sheet
for discussion of Boot PROM. (Must be initialized by OEM before shipping adapter.)
Bit 13 StreamTransfer Mode - Refer to the CS8900A Data Sheet for description of SteamTransfer
mode. Default is disabled.
Bit 12 DMA Burst - Refer to BusCTL Register of the CS8900A Data Sheet for a discussion of
DMA Burst control. Default is enabled.
Bit 11 RxDMA Only - Refer to the CS8900A Data Sheet for a description of RxDMA Only mode.
Default is disabled.
Bit 10 Auto RxDMA - Refer to the CS8900A Data Sheet for a description of Auto RxDMA mode.
Default is disabled.
Bit 9 DMA Buffer Size - Refer to the CS8900A Data Sheet for a discussion of DMA Buffer size.
Default is 16K.
Bit 8 IOCHRDY Enable - Refer to the BusCTL Register, of the CS8900A Data Sheet for a dis-
cussion of IOCHRDY control. Default is enabled.
Bit 7 UseSA - Refer to the BusCTL Register, of the CS8900A Data Sheet for a discussion of Us-
eSA control. Default is enabled.
Bits 6-4 DMA Channel Select - Refer to the CS8900A Data Sheet for a discussion of DMA channel
selection for the CS8900A. Default is disabled.
Bits 3-0 IRQ Channel Select - Refer to the CS8900A Data Sheet for the typical ISA Bus, CS8900A
pin to pin connection. Cirrus’ pre-written drivers expect the pins to be connected as de-
scribed in the datasheet when running in an x86 system.
Addr Word Description
1Ch 0100h 2 MSB of address (byte reversed)
1Dh 0302h Middle 2 bytes (byte reversed)
1Eh 0504h 2 LSB of address (byte reversed)