Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 19)

UG029, September 6, 2013 19
completed thru SBUS. During write it is valid for one cycle
to indicate the end of the transfer. This is asserted for 4-
cycles to validate 8-bit data at the end of read.
o_sbus_data[1:0] Out
Contains read data for 4-cycles when o_sbus_ack is
asserted.
pma_[11:0]_i_sbus_
data[1:0]
In Input serial data interface for PHY PMA internal registers.
pma_0_i_sbus_req In
Request signal for starting a read or write transaction on the
serial interface for PHY PMA internal registers.
pma_0_o_sbus_ack Out
Acknowledge signal for a complete read or write operation
on the serial interface for PHY PMA internal registers.
pma_0_o_sbus_dat
a[1:0]
Out Output serial data interface for PHY PMA internal registers.
SerDes (off-chip) Interface
Table 8 – FPGA SerDes Off-Chip I/O pins (all synchronous to serdes_ck_ref_*)
Signal Name Mode Description
serdes_ck_ref_m[11:0] In Management Data Clock.
serdes_ck_ref_p[11:0] In Management Data Input.
serdes_rx_m[11:0] In Management Data Output.
serdes_rx_p[11:0] In Management Data Output Enable (active low).
serdes_tx_m[11:0] Out Management Data transaction is ongoing
serdes_tx_p[11:0] Out Management Data transaction is ongoing
Transmitted Frame Status
Table 9 – Transmitted Frame Status (all synchronous to ff_tx_clk[0])
Signal Name Mode Description
tx_ts_val Out
Timestamp Valid. Asserted for one ref_clk clock
cycle to indicate that tx_ts_id and tx_ts are valid.
The timestamp can be mapped to any segment of
FIFO group 0 (10G: SEG0-3, 40G: SEG0, 100G:
SEG0).
The signal is not asserted for internally generated
Pause frames.
tx_ts_id[3:0] Out
Frame Identifier. The value that was provided by the
application at ff_tx_id[3:0] for the frame.
tx_ts[31:0] Out
Frame Timestamp Value. Transmit timestamp value
for the frame sent with the sequence number set on
tx_ts_id.
Timestamp Timer
Table 10 – Timestamp Timer (all synchronous to ts_clk)
Signal Name Mode Description
ts_clk In
Clock for the timestamp timer.
Maximum frequency is 1/4 of the ref_clk to allow for
proper clock domain synchronization.
frc_in[31:0] In Current value of an externally provided free running