Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 26)

26 UG029, September 6, 2013
Clock Distribution
The clock frequency of the SerDes interface depends on the selected SerDes datapath width
(synthesis option). The ACE GUI allows the user to pick one of several frequencies.
The Figure below shows the system clock distribution for the 10/40/100 Gigabit Ethernet
MAC and PCS Core for the 20-Bit SerDes interface.
Figure 6: System clock distribution for the 20-Bit SerDes interface
On the FIFO interface, 3 individual clock signals are provided for both transmit
(ff_tx_clk[2:0]) and receive (ff_rx_clk[2:0]). When 100G mode of operation is selected, the
clock signals ff_tx_clk[2:0] and ff_rx_clk[2:0] and their respective reset lines have to be driven
from the same clock and reset sources. The system clock distribution diagram below shows
an example implementation for the external clock and reset multiplexers.