Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 51)

UG029, September 6, 2013 51
PMA Management Interface
Power State Descriptions
The PMA supports the following 5 power States. Power state transitions are not allowed to
occur, while the following events are still under way:

Rate Change

Data Width Change
The user must ensure that any previously initiated event completes, prior to beginning a
power state change.
Table 27 – SerDes Power State Descriptions
Power
State
Power State Description
Power
Down
The power-down power state disables the lane completely. All analog blocks are
placed in power down. Receiver input terminations are set to high impedance. All
digital blocks are placed in reset. All clocks are switched over to keep-alive clock
to ensure basic functionality is supported to exit this power state.
P2
The Coma State supports limited functionality: Signal detection and transmit
beaconing are supported as required by standards such as PCIe. All remaining
analog blocks are powered down; all digital blocks are in reset. All clocks are
switched over to keep-alive clock to ensure basic functionality is supported to exit
this power state.
P1
The Slumber state is used as a fast power down state, which has a quick
recovery time. The synthesizer must be powered up prior to entering the Slumber
state. In this state, the transmit driver is disabled in an ultra-low power Doze
Mode. The entire transmit path is disabled and relevant clocks are gated. The
receiver path is still completely powered down. All clocks derived from the PLL
are switched over to their respective clocks, from the keep-alive clock, in a glitch
free manner.
P0s
The Doze state is a low power state for the transmit portion of the PMA. The CDR
and the receiver are now completely powered up. The PMA can be receiving data
in this state, however it is not transmitting data in this state. As a result, the
transmit path is reset, and the output driver is disabled in an ultra-low-power Doze
Mode. All clocks are now fully active and have switched over to their respective
clocks, from the keep-alive clock, in a glitch free manner. The receiver Ready
signal OCTL_PCS_RXREADY_Lx_A is asserted in this state.
P0
The Ready state is the fully active state for the PMA. Both the transmit and
receive data paths are fully capable to transmit and receive data. All clocks are
now fully active and have switched over to their respective clocks, from the keep-
alive clock, in a glitch free manner. The transmitter Ready signal
OCTL_PCS_TXREADY_Lx_A is asserted in this state.
Note: The PHY power state can also be controlled via the PMA memory register interface