Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 5)

UG029, September 6, 2013 5
Transmit Timestamping ....................................................................................................... 58
MAC & PCS Configuration Registers ............................................................. 59
MAC & PCS Register Overview ........................................................................................... 59
Channelized MAC Registers ................................................................................................ 61
COMMAND_CONFIG Register Bit Definitions .............................................................................. 67
STATUS Register Bit Definitions .................................................................................................. 70
10G MAC SGMII PCS Register Map ................................................................................... 71
1000Base-X / SGMII PCS .................................................................................................... 71
1000Base-X/SGMII PCS Registers Description ........................................................................... 73
Global Registers .................................................................................................................. 77
Core Configuration Registers ....................................................................................................... 77
VLAN Tag Configuration Registers .............................................................................................. 78
Channelized PCS Registers................................................................................................. 79
Auto-Negotiation Registers .................................................................................................. 87
Control Register Bits (KXAN_CONTROL) .................................................................................... 89
Status Register Bits (KXAN_STATUS) ......................................................................................... 89
Ability Register Bits (KXAN_ABILITY / KXAN_REM_ABILITY) ..................................................... 90
Next page Ability Register Bits (AN_XNP / LP_AN_XNP) ............................................................ 91
PMA Registers ................................................................................................. 93
PMA State Control ............................................................................................................... 93
Memory Bus (Membus) Interface ................................................................................................. 93
Memory Address Decoding .......................................................................................................... 93
PMA Receive Equalization Registers ................................................................................... 93
TX/RX Lane Receive Equalization Registers................................................................................ 94
Common/Synth Lane Receive Equalization Registers .................................................................. 96
PMA Transmit Control Registers .......................................................................................... 96
TX/RX Lane Transmit Control Registers ...................................................................................... 96
Common/Synth Lane Transmit Control Registers ........................................................................ 97
PMA Adaptive Equalizer Registers ...................................................................................... 98
TX/RX Lane Adaptive Equalizer Registers ................................................................................... 98
Common/Synth Lane Adaptive Equalizer Registers ..................................................................... 99
Statistics Data Registers .............................................................................. 102
Overview ............................................................................................................................ 102
IEEE 802.3 Management Package .................................................................................... 102
IETF Management Information Base (MIB, MIB-II) Objects ............................................... 102
IETF Remote Network Monitoring ...................................................................................... 102
Receive Statistics Vector ................................................................................................... 103
Transmit Statistics Vector .................................................................................................. 105