Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 67)

UG029, September 6, 2013 67
Mode.
See “
10G MAC SGMII PCS Register Map ” on page
71.
224-
255
380 -
3fc
reserved R(W)
Note: The PCS registers are 32 registers
within the addresses at 0x300 .. 0x37f. They
are mirrored at 0x380..0x3ff for write
accesses but not for read. Hence write
accesses to this register area should be
omitted.
COMMAND_CONFIG Register Bit Definitions
Table 35 – COMMAND_CONFIG Register Description
Bit# Bit Name Description
0 TX_ENA
MAC Transmit Path Enable. Should be set to '1' to
enable the MAC transmit path, should be set to '0' (Reset
value) to disable the MAC transmit path.
1 RX_ENA
MAC Receive Path Enable. Should be set to '1' to enable
the MAC receive path, should be set to '0' (Reset value)
to disable the MAC receive path.
2 reserved unused
3 WAN_MODE
Enable WAN Mode. Sets WAN mode (1) or LAN mode
(0, default) of operation.
Note: When changing the mode, verify correct setting of
the transmit Inter-Packet-Gap (IPG) in register
TX_IPG_LENGTH.
Note: This bit is only available in 10G mode of operation.
It is reserved in 40G and 100G mode of operation.
4 PROMIS_EN
Enable MAC Promiscuous Operation. If set to '1', all
frames are received without any MAC address filtering. If
set to '0' (Reset value), unicast frames with a destination
address not matching the Core MAC address
(programmed in registers MAC_ADDR_0 and
MAC_ADDR_1) are rejected.
5 PAD_EN
Enable Frame Padding Removal in receive path. If set to
'1', padding is removed before the frame is conveyed to
the MAC client application. If set to '0' (Reset value), no
padding is removed on receive by the MAC.
Note: Not available in this implementation.
6 CRC_FWD
Terminate / Forward Received CRC. If set to '1', the
CRC field of received frames is forwarded with the frame
to the user application. If set to '0' (Reset value), the
CRC field is stripped from the frame.
Note: If padding (Bit PAD_EN set to ‘1’) is enabled,
CRC_FWD is ignored.