Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 39)

UG029, September 6, 2013 39
The transmit FIFO interface is protected against the following invalid signaling conditions:

Missing SOP: All ff_tx_wren assertions prior to ff_tx_sop assertion are ignored

Missing EOP: Assertion of ff_tx_sop within a frame (i.e. no previous EOP
occurred) is ignored. This error condition is latched and will cause the frame to be
sent with an error indication (i.e. as if the ff_tx_err signal was asserted)
FIFO Interface Receive Operation
On the receive FIFO interface, the MAC Core initiates frame transfers to the user application.
The Core provides data on the FIFO interface based on the configuration. Note that for
improved readability, the following figures only show data transfers for segment 0 in 100G
mode of operation. For all other segments in other configuration modes, the corresponding
signals are provided accordingly.
An internal credit counter is used to determine when the user application is ready to accept
data. Upon writing of the credit trigger register, the credit counter is loaded with a
programmable initial credit value. For each valid output cycle, the credit counter is debited
by 1. When the credit counter reaches 0, the MAC Core stops sending data to the output
FIFO. The credit counter is issued credits when the user reads the FIFO by asserting the
ff_rx_rdy[0] signal. The assertion of ff_rx_rdy[0] signals to the FIFO interface that
the user has consumed the ff_rx_data currently at the output of the FIFO. Upon the
assertion of ff_rx_rdy[0], the MAC Core resumes transmitting data to the user
application. Valid data is associated with a valid signal (ff_rx_dval[0]). If the user
application is fast enough to receive the output data continuously, it may tie the
ff_rx_rdy[0] signal high and consume the FIFO output data when the valid signal
ff_rx_dval[0] is high. If the user application needs to pause the output FIFO, it may
deassert ff_rx_rdy[0], while also monitoring the FIFO’s almost-full flag
ff_rx_afull[0] to prevent the output FIFO from overflowing.
The MAC Core asserts a start of frame signal (ff_rx_sop[0]) at the beginning of a frame
and an end of frame signal (ff_rx_eop[0]) with the last word of the frame. In addition, a
word modulo (ff_rx_mod[5:0]) and status information (ff_rx_err_stat[23:0]) is
provided with the last word of the frame. Note that the receive status
ff_rx_err_stat[23:0] can only be mapped to any segment of FIFO group 0 (10G: SEG0-
3, 40G: SEG0, 100G: SEG0).
Optionally a user specific frame preamble is provided on ff_rx_preamble[55:0]. To
indicate a valid preamble, ff_rx_preamble_val is asserted together with ff_rx_sop[0].
Note that the user defined preamble signals can only be mapped to any segment of FIFO
group 0 (10G: SEG0-3, 40G: SEG0, 100G: SEG0).