Achronix Speedster22i 10G/40G/100G Ethernet - Manual (Page 61)

UG029, September 6, 2013 61
Channelized MAC Registers
The Channelized MAC Registers are located on pages 0 through 11. Each segment has its
own set of MAC configuration, control and status registers. The register map of each register
set is identical and shown below.
The following register map shows a 32-Bit register implementation. The address is given in
steps of 4 to indicate the 32-bit alignment of the register space in a usual host processor
memory map.
Bit 0 is the least significant bit and all registers are initialized to zero upon reset except when
stated otherwise.
The following register types are used:

RW: Read/write register. Unused bits should be written with 0 and ignored on read.

RO: Read only, write has no effect

WO: Write only, returns all zero on read

ROR: Read only and Reset. The value is reset to zero after it has been read.
Table 33 – Channelized MAC Register Map
Reg#
Addr
(hex)
Register Name Type Description
0 00 REVISION RO
7:0: Core Revision.
15:8: Core Version.
31:16: Programmable Customer Revision
1 04 SCRATCH RW
The Scratch Register provides a memory
location to test the register access.
2 08 COMMAND_CONFIG RW
Control/Configuration of the core.
See “COMMAND_CONFIG Register Bit
Definitions
” on page 67.
3 0C MAC_ADDR_0 RW
The lower 32-Bit of the 48-Bit MAC Address.
Bit 0 is LSB.
4 10 MAC_ADDR_1 RW
The upper 16-Bit of the 48-Bit MAC Address.
Bit 0 is Bit 32 of MAC address.
Bits 31:16 are unused and always set to ‘0’.
5 14 FRM_LENGTH RW
13:0: Maximum supported frame length.
The MAC supports any frame size up to
16352 bytes (0x3fe0). Typical settings are
1518 for standard. Set to 1536 after Reset.
Bits 31:14 are unused and always set to ‘0’.
6 18 reserved -- unused
7 1C RX_FIFO_SECTIONS RW
15:0: RX section available threshold, reset
value is 0x3.
31:16: RX section empty threshold, reset
value is 0x00.
All threshold values are in steps of segment
data words (10G: 32-bit, 40G: 128-bit, 100G:
384-bit).
8 20 TX_FIFO_SECTIONS RW
15:0: TX section available threshold, reset
value is 0x3.
31:16: TX section empty threshold, reset
value is 0x0.
All threshold values are in steps of segment
data words (10G: 32-bit, 40G: 128-bit, 100G: