CANOGA PERKINS 2240 Fiber Optic Modem - Manual (Page 38)

2240 Fiber Optic Modem User Manual Chapter 3 Mode and Rate Selection
Consideration of Propagation Delays
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Figure 3-3 RS-449/422 Null Cable Diagram for 2240
NOTE: If the customer's DCE does not support TT (or equivalent) lead, a buffered
interface may be needed to realign the data or the extra clock function can
be used (refer to section 4.9). Canoga Perkins offers a wide selection of
buffered interfaces.
3.6 Consideration of Propagation Delays
Whenever the modem is sending a transmit clock to the DTE, it is important to understand the
effect of the time required for that clock to propagate from the modem to the DTE.
Clock-to-Data phasing is particularly important in any synchronous data link. The modem expects
the data to be valid (unchanging) at the point in time when the clock is transitioning to "clock" the
data.
When the modem is the source of the transmit clock, there is a finite time delay before that clock
arrives at the DTE to clock its transmitter. There is another time delay before the data from the
DTE arrives back at the modem.
Since the modem uses its own clock signal to align the data, there is a potential for these delays
to make the data invalid at the point of re-alignment. This problem only occurs at high data rates
and if the cable to the DTE is very long or has high capacitance.
In such cases it is desirable to use a clock signal sourced from the DTE, because it will
experience the same time delays as the data signal. To get an aligned clock signal, loop the clock
from the ST to TT leads at the DTE end of the cable (if the DTE does not do this by default).
Table 3-6 lists delay times for sub-DSO rates.