Document Outline

• TABLE OF CONTENTS
• SECTION 1: INTRODUCTION
• SECTION 2: ORDERING INFORMATION
• SECTION 3: ARCHITECTURE
  • ALU
  • Special-Function Registers
    • Accumulator
    • B Register
    • Program Status Word
    • Data Pointer(s)
    • Stack Pointer
    • I/O Ports
    • Timer/Counters
    • UARTs
  • Scratchpad Registers (RAM)
    • Stack
    • Working Registers
    • Program Counter
    • Address/Data Bus
    • Watchdog Timer
    • Power Monitor
    • Interrupts
    • Timing Control
  • Flash Memory
• SECTION 4: PROGRAMMING MODEL
  • Memory Organization
  • Memory Map
  • Register Map
  • Bit Addressable Locations
  • Working Registers
  • Stack
  • Addressing Modes
    • Register Addressing
    • Direct Addressing
    • Register Indirect Addressing
    • Immediate Addressing
    • Register Indirect with Displ...
    • Relative Addressing
    • Page Addressing
    • Extended Addressing
  • Program Status Flags
  • Special-Function Register Lo...
  • Special-Function Registers
    • Port 0 (P0)
    • Stack Pointer (SP)
    • Data Pointer Low 0 (DPL)
    • Data Pointer High 0 (DPH)
    • Data Pointer Low 1 (DPL1)
    • Data Pointer High 1 (DPH1)
    • Data Pointer Select (DPS)
    • Power Control (PCON)
    • Timer/Counter Control (TCON)
    • Timer Mode Control (TMOD)
    • Timer 0 LSB (TL0)
    • Timer 1 LSB (TL1)
    • Timer 0 MSB (TH0)
    • Timer 1 MSB (TH1)
    • Clock Control (CKCON)
    • Port 1 (P1)
    • External Interrupt Flag (EXIF)
    • Timer and Serial Port Clock ...
    • Serial Port 0 Control (SCON0)
    • Serial Data Buffer 0 (SBUF0)
    • Revision ID (RID)
    • Address Control (ACON)
    • Port 2 (P2)
    • Interrupt Enable (IE)
    • Slave Address Register 0 (SA...
    • Slave Address Register 1 (SA...
    • Port 3 (P3)
    • Interrupt Priority 1 (IP1)
    • Interrupt Priority 0 (IP0)
    • Slave Address Mask Enable Re...
    • Slave Address Mask Enable Re...
    • Serial Port 1 Control (SCON1)
    • Serial Data Buffer 1 (SBUF1)
    • ROM Size Select (ROMSIZE)
    • Power Management Register (PMR)
    • Status Register (STATUS)
    • Timed Access Register (TA)
    • Timer 2 Control (T2CON)
    • Timer 2 Mode (T2MOD)
    • Timer 2 Capture LSB (RCAP2L)
    • Timer 2 Capture LSB (RCAP2H)
    • Timer 2 LSB (TL2)
    • Timer 2 MSB (TH2)
    • Program Status Word (PSW)
    • Watchdog Control (WDCON)
    • Accumulator (A or ACC)
    • Extended Interrupt Enable (EIE)
    • B Register (B)
    • Extended Interrupt Priority ...
    • Extended Interrupt Priority ...
• SECTION 5: CPU TIMING
  • Oscillator
  • XTAL1
  • XTAL2
  • Oscillator Characteristics
  • Crystal Selection
  • System Clock Divide Control
  • Instruction Timing
    • Single-Byte Instructions
    • 2-Byte Instructions
    • 3-Byte Instructions
  • Nonpage Mode External Timing
  • Page Mode 1 External Timing—...
  • Page Mode 1 External Timing—...
  • Page Mode 1 External Timing—...
  • Page Mode 2 External Timing—...
  • Comparison to the 8051
• SECTION 6: MEMORY ACCESS
  • Internal Flash Memory
  • ROMSize Feature
  • Flash Security Block/Lock Bits
  • Option Control Register Byte
  • Internal SRAM Memory
  • Program Memory Interface—Non...
  • Program Memory Interface—Pag...
    • Page Mode 1 Bus Structure
    • Page Mode 2 Bus Structure
  • Data Memory Interface
    • External Data Memory Interfa...
    • External Data Memory Interfa...
  • Page Mode 1 Data Memory Timi...
  • Page Mode 1 Data Memory Timi...
  • Page Mode 1 Data Memory Timi...
  • Page Mode 2 Data Memory Timi...
  • Data Memory Access
• SECTION 7: POWER MANAGEMENT
  • Power Management Summary
    • Precision Voltage Monitor
    • Early-Warning Power-Fail Int...
    • Power-Fail Reset
    • Power-On Reset
    • Bandgap Select
    • Watchdog Wake-Up From Idle
  • Power Saving
    • Clock Divide Control
    • Idle Mode
    • Stop Mode
    • Ring Oscillator Wake-Up From...
    • Speed Reduction
    • Power Management Modes
    • Power Management Mode Timing
    • PMM and Peripheral Functions
  • Switchback
  • Clock Source Selection
  • Ring Oscillator Resume From ...
• SECTION 8: RESET CONDITIONS
  • Reset Sources
  • Power-On/Power-Fail Reset
  • Watchdog Timer Reset
  • Oscillator Fail-Detect Reset
  • External Reset
  • Determining The Cause Of a R...
• SECTION 9: INTERRUPTS
  • Interrupt Overview
  • Interrupt Sources
    • External Interrupts
    • Timer Interrupts
    • Serial Communication Interrupts
    • Power-Fail Interrupt
    • Simulated Interrupts
  • Interrupt Priorities
    • Interrupt Register Conflicts
  • Interrupt Acknowledge Cycle
  • Interrupt Latency
• SECTION 10: I/O PORTS
  • Parallel I/O
    • Port 0
    • Port 2
    • Port 1
    • Port 3
    • Alternate Functions of Ports...
  • Read-Modify-Write
  • Output Functions
  • Input Functions
• SECTION 11: PROGRAMMABLE TIMERS
  • 16-Bit Timers
  • Timer 0, Timer 1 Modes
  • Mode 0
  • Mode 1
  • Mode 2
  • Mode 3
  • Timer 2 Modes
    • 16-Bit Timer/Counter with Op...
    • 16-Bit Autoreload Timer/Counter
    • Up/Down-Count Autoreload Tim...
    • Baud-Rate Generator
    • Timer Output Clock Generator
  • Time-Base Selection
  • Watchdog Timer
• SECTION 12: SERIAL I/O
  • Serial Mode Summary
  • Mode 0
  • Mode 1
  • Mode 2
  • Mode 3
  • Serial Port Initialization
  • Baud Rates
    • Mode 0
    • Mode 2
    • Mode 1 or 3
      • Using Timer 1 for Baud-Rate ...
      • Using Timer 2 for Baud-Rate ...
  • Serial I/O Description
    • Mode 0
    • Mode 1
    • Mode 2
    • Mode 3
  • Framing Error Detection
  • Multiprocessor Communication
• SECTION 13: TIMED-ACCESS PROTECTION
  • Protected Bits
  • Protection Scheme
  • Timed-Access Protects Watchdog
• SECTION 14: INSTRUCTION SET DETAILS
• SECTION 15: PROGRAM LOADING
  • ROM Loader Mode
    • Invoking the ROM Loader Mode
    • Exiting the Loader
    • Serial Program Load Operation
  • Command Line Interface
  • Command Line Syntax
  • Command Summaries
  • Error Messages
  • Parallel Programming Mode
  • User Code In-Application Pro...
  • Intel Hex File Format
• REVISION HISTORY