Table 3-2: interrupt source set up – ADLINK PCI-7260 User Manual
Page 35
Register Format
25
1 : enable
0 : disable
CH0 Int_EN (bit 9): Write/Read
DI channel 0 interrupt enable control
1 : enable
0 : disable
CH1 Int_EN (bit 10): Write/Read
DI channel 1 interrupt enable control
1 : enable
0 : disable
WDT Int_EN (bit 15): Write/Read
WDTimer counter/interrupt enable control
1 : enable
0 : disable
The following table shows all possible combinations of interrupt
source.
Table 3-2: Interrupt Source Set Up
Interurpt type Bit 15 Bit 10 Bit 9 Bit 8
IRQ source
IRQ trigger condition
Disable
0
0
0
0
Interrupt disable
--
Mode 1
0
0
0
1
COS interrupt
Change of state in
the enabled channel
Mode 2
0
0
1
0
Ch.0 interrupt
enable
Rising edge of DI
channel 0
Mode 2
0
1
0
0
Ch.1 interrupt
enable
Rising edge of DI
channel 1
Mode 2
0
1
1
0
Ch.0 & 1 interrupt
enable
Rising edge of DI
channel 0 or 1
Mode 3
1
0
0
0
WDTimer Couner
interrupt enable
WDTimer is overflow
Forbidden
X
0
1
1
Not allowed (dis-
able)
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