ADLINK PXIS-2508 - Manual (Page 26)

16 Chassis Overview
Trigger Bus
The trigger bus is an 8-line bus that connects all PXI slots in the
same PCI segment. You can use the trigger bus as an intermodule
synchronization mechanism. PXI modules can transmit trigger or
clock signals to one another through the trigger bus, enabling pre-
cise timed responses to asynchronous external events that the
system is monitoring or controlling.
System Reference Clock
The backplane comes with a PXI 10 MHz system reference clock
(PXI_CLK10). An independent buffer (having source impedance
matched to the backplane and a skew of less than 1 ns between
slots) drives the clock signal generated from a high-precision oscil-
lator to each peripheral slot. You can use this common reference
clock signal to synchronize multiple modules in a PXI chassis.