3 trigger source and trigger modes, Trigger source and trigger modes, Figure 3-2 – ADLINK PCIe-9852 User Manual
Page 26: Linked list of pci address dma descriptors, Figure 3-3, Trigger architecture of the pcie-9852
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16
Operations
Figure 3-2: Linked List of PCI Address DMA Descriptors
3.3 Trigger Source and Trigger Modes
This section details PCIe-9852 triggering operations.
Figure 3-3: Trigger Architecture of the PCIe-9852
Local Memory
( FIFO)
PCI Express Bus
First PCI Address
First Dual Address
Transfer Size
Next Descriptor
PCI Address
Dual Address
Transfer Size
Next Descriptor
PCI Address
Dual Address
Transfer Size
Next Descriptor
Trigger
Decision
Software trigger
Digital trigger input
To Internal FPGA circuits
SSI
Trigger Output
MU
X
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