ADLINK PCIe-9852 - Manual (Page 7)

List of Figures vii
PCIe-9852
List of Figures
Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp............... 3
Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp.................. 4
Figure 1-3: PCIe-9852 Schematic................................................. 8
Figure 1-4: PCIe-9852 I/O Array ................................................... 9
Figure 3-1: Analog Input Architecture of the PCIe-9852 ............. 13
Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 16
Figure 3-3: Trigger Architecture of the PCIe-9852...................... 16
Figure 3-4: External Digital Trigger ............................................. 17
Figure 3-5: Post-Trigger Acquisition ........................................... 18
Figure 3-6: Delayed Trigger Mode Acquisition............................ 19
Figure 3-7: Pre-Trigger Mode Acquisition ................................... 19
Figure 3-8: Middle Trigger Mode Acquisition .............................. 20
Figure 3-9: Re-Trigger Mode Acquisition .................................... 21
Figure 3-10: PCIe-9852 Clock Architecture .................................. 21
Figure 3-11: PCIe-9852 Timebase Architecture ........................... 22
Figure 3-12: Basic Digitizer Acquisition Timing............................. 23
Figure 3-13: Varying Sampling Rates
by Adjusting Scan Interval Counter .......................... 24
Figure 3-14: Card Number Configuration Switch .......................... 27