ADLINK PCIe-9852 - Manual (Page 32)

22 Operations
3.5.2 External Reference Clock
The PCIe-9852 can choose an external clock source for use as a
reference clock. When an external clock reference is selected, the
synthesizer input will switch to the clock source at SMA connector
CLK IN, and generate precisely 200MHz clock for ADC. The fre-
quency of clock source is restricted to 10MHz.
3.5.3 External Sampling Clock
The PCIe-9852 can further choose an external clock source as
ADC sampling clock. When an external sampling clock is selected,
the ADC sampling frequency switches to the clock source at SMA
Connector CLK IN, and clock source frequency is available from
40MHz to 200MHz.
3.6 ADC Timing Control
3.6.1 Timebase Architecture
Figure 3-11: PCIe-9852 Timebase Architecture
3.6.2 Basic Acquisition Timing
The PCIe-9852 commences acquisition upon receipt of a trigger
event originating with software command, external digital trigger,
or the PXI Trigger Bus. The Timebase is a clock provided to the
ADC and acquisition engine for essential timing. The Timebase is
ADC
ADC Output
Onboard
200 MHz
Oscillator
200 MHz
X2
Multiplier
PLL
400 MHz
200 MHz
FPGA
For ADC
Data Bus
For ADC
state
machine