Altera Nios II C2H Compiler - Manual (Page 17)

Altera Corporation 9.1 1–11
November 2009 Nios II C2H Compiler User Guide
Introduction to the C2H Compiler
The software wrapper, executing on the Nios II processor, controls the
accelerator by reading and writing the register interface. From the
perspective of the calling function, the result of calling the software
wrapper is functionally the same as calling the original C function. The
basic operation of the software wrapper is as follows:
1. Sets up parameters for the accelerator, similar to passing variables to
the original, unaccelerated function.
2. Optionally flushes the processor's data cache to avoid cache
coherency problems. Flushing the data cache might be necessary if
the accelerator accesses the same memory that the processor does.
3. Starts the accelerator. Once an accelerator is running, it can return a
value, terminate, or run continuously, depending on the design of
the C source code.
4. Polls registers in the accelerator hardware to determine when the
task completes.
5. If the function returns a result, reads the result value, and returns it
to the calling function.
One-to-One Mapping From C Syntax to Hardware Structure
The C2H Compiler maps each element of C syntax to an equivalent
hardware structure using straightforward translation rules that directly
instantiate hardware resources based on the input C code. Once familiar
with the C2H Compiler mappings, you can control the generated
hardware structure with simple changes to your C source.
The following are examples of how the C2H Compiler translates C to
hardware:
■ Mathematical operators (such as + , - , * , >> ) become direct hardware
equivalent circuits (such as add, subtract, multiply and shift circuits).
These circuits might be shared between operations, depending on
the degree of parallelism inherent in the C code.
■ Loops (such as for , while , do-while ) become state machines that
iterate over the operations inside the loop, until the loop condition is
exhausted.
■ Pointer dereferences and array accesses (such as *p , array[i][j] )
become Avalon-MM master ports that access the same memory that
the processor does.
■ Statements not dependent on the result of a previous operation are
scheduled as early as possible, allowing parallel execution to the
extent possible.