Dynamic tx clock switching, Dynamic tx clock switching -7 – Altera SDI II MegaCore User Manual
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Dynamic TX Clock Switching
The dynamic TX clock switching feature allows you to dynamically switch between NTSC and PAL
transceiver data rates for all video standards except SD-SDI. The dynamic TX clock switching enables an
SDI video equipment to operate on NTSC or PAL.
You can choose to switch the TX clocks through one of these two methods:
• Instantiate an alternate TX PLL and supply two different clocks to the two PLLs. Switch between the
primary PLL and the alternate PLL for transmission.
• Use the primary PLL with two reference input clocks. The PLL switches between these two clocks for
transmission.
To implement this feature, you are required to provide two reference clocks (
xcvr_refclk
and
xcvr_refclk_alt
) to the SDI II IP core. The frequency of the reference clocks must be assigned to 148.5
MHz and 148.35 MHz in any assignment order.
The TX PLL select signal (
ch1_{tx/du}_tx_pll_sel
) is an input control signal that you provide to the
core and the transceiver reconfiguration controller to select the desired clock input for the hard
transceiver.
• Set
ch1_{tx/du}_tx_pll_sel
to 0 to select
xcvr_refclk
• Set
ch1_{tx/du}_tx_pll_sel
to 1 to select
xcvr_refclk_alt
To dynamically switch between the two reference clocks, you need to implement a simple handshaking
mechanism. The handshake is initiated when the reconfiguration request signal (
ch1_{tx/
du}_tx_start_reconfig
) is asserted high. This signal must remain asserted until the reconfiguration
process completes. The reconfiguration process completes when the reconfiguration done signal
(
ch1_{tx/du}_tx_reconfig_done
) is asserted high. The TX PLL select signal (
ch1_{tx/
du}_tx_pll_sel
) needs to be stable throughout the reconfiguration process.
To complete the handshaking process, you must deassert the reconfiguration request signal (
ch1_{tx/
du}_tx_start_reconfig
) upon assertion of the reconfiguration done signal (
ch1_{tx/
du}_tx_reconfig_done
). The dynamic TX clock switching only takes effect after the
tx_rst
is asserted
high and deasserted low accordingly.
UG-01125
2015.05.04
Dynamic TX Clock Switching
2-7
SDI II IP Core Overview
Altera Corporation